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    Fast invalidation scheme for caches
    1.
    发明授权
    Fast invalidation scheme for caches 有权
    缓存的快速无效方案

    公开(公告)号：US06438658B1

    公开(公告)日：2002-08-20

    申请号：US09609072

    申请日：2000-06-30

    申请人： Harikrishna B. Baliga ,  Subramaniam Maiyuran ,  Salvador Palanca

    发明人： Harikrishna B. Baliga ,  Subramaniam Maiyuran ,  Salvador Palanca

    IPC分类号： G06F1200

    CPC分类号： G06F12/0891

    摘要： A method and apparatus for single cycle, cache line invalidation within a cache memory is described. The method includes enabling memory cells within a cache state array of the cache memory. An invalid state is then written to each memory cell within the cache state array of the cache memory. The enabling of the memory cells within the cache state array of the cache memory occurs during a first phase of a clock cycle. While the writing of the invalid state to each memory cell within the cache state array of the cache memory occurs during a second phase of the clock cycle. Consequently, cache line invalidation of each cache line within the cache memory occurs within a single clock cycle formed by the first phase of the clock cycle and the second phase of the clock cycle. In partial invalidation of the cache memory is possible by way-subdividing the cache state array or set-subdividing the cache state array. One shot or single cycle cache line invalidation reduces the total time required for invalidation of all cache lines within the cache memory to just a clock cycle. The implementation is simple with minimal changes to the cache array limited only to those cells that store the state information of the cache lines. Since many system operations necessitate invalidation of the entire cache, one-shot invalidation clearly improves the system performance with no significant impact on the die size.

    摘要翻译： 描述了用于单周期，高速缓冲存储器内的高速缓存行无效的方法和装置。 该方法包括启用高速缓冲存储器的高速缓存状态阵列内的存储单元。 然后将无效状态写入高速缓冲存储器的高速缓存状态阵列内的每个存储单元。 高速缓冲存储器的高速缓存状态阵列内的存储单元的使能在时钟周期的第一阶段期间发生。 当在时钟周期的第二阶段期间，将无效状态写入到高速缓冲存储器的高速缓存状态阵列内的每个存储器单元。 因此，高速缓冲存储器内的每个高速缓存行的高速缓存行无效发生在由时钟周期的第一阶段和时钟周期的第二阶段形成的单个时钟周期内。 通过对高速缓存状态数组进行细分，或者对高速缓存状态数组进行分组，可以使高速缓冲存储器部分失效。 单次或单周期高速缓存行无效将将缓存中所有高速缓存行无效的总时间减少到仅仅一个时钟周期。 该实现是简单的，对缓存阵列的最小变化仅限于存储高速缓存行状态信息的那些单元。 由于许多系统操作需要使整个高速缓存无效，一次性无效显然提高了系统性能，对芯片尺寸没有显着的影响。

    Cache dynamically configured for simultaneous accesses by multiple computing engines
    3.
    发明授权
    Cache dynamically configured for simultaneous accesses by multiple computing engines 有权
    缓存动态配置为同时访问多个计算引擎

    公开(公告)号：US06665775B1

    公开(公告)日：2003-12-16

    申请号：US09667688

    申请日：2000-09-22

    申请人： Subramaniam Maiyuran ,  Salvador Palanca

    发明人： Subramaniam Maiyuran ,  Salvador Palanca

    IPC分类号： G06F1208

    CPC分类号： G06F12/0848 ,  G06F12/084 ,  G06F12/0846

    摘要： A cache has an array with single ported cells and is dynamically accessible simultaneously by multiple computing engines. In a further embodiment, the cache also has a tag array including a first address input, a second address input, and a shared mode input, and a data array electrically coupled to the tag array and including a first address input, a second address input, and a shared mode input.

    摘要翻译： 缓存具有单个移植单元的阵列，并且可由多个计算引擎同时动态访问。 在另一实施例中，高速缓存还具有包括第一地址输入，第二地址输入和共享模式输入的标签阵列，以及电耦合到标签阵列的数据阵列，并且包括第一地址输入，第二地址输入 ，和共享模式输入。

    System and method for cache sharing
    9.
    发明授权
    System and method for cache sharing 有权
    用于缓存共享的系统和方法

    公开(公告)号：US06801208B2

    公开(公告)日：2004-10-05

    申请号：US09750750

    申请日：2000-12-27

    申请人： Jagganath Keshava ,  Vladimir Pentkovski ,  Subramaniam Maiyuran ,  Salvador Palanca ,  Hsin-Chu Tsai

    发明人： Jagganath Keshava ,  Vladimir Pentkovski ,  Subramaniam Maiyuran ,  Salvador Palanca ,  Hsin-Chu Tsai

    IPC分类号： G09G536

    CPC分类号： G06F3/14 ,  G06F12/084 ,  G09G5/001 ,  G09G5/393 ,  G09G2330/021 ,  G09G2350/00

    摘要： A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.

    摘要翻译： 一种用于缓存共享的系统和方法。 该系统是包括处理器核心和图形引擎的微处理器，每个耦合到高速缓冲存储器。 微处理器还包括一个驱动程序，用于指示高速缓冲存储器如何由处理器核心和图形引擎共享。 该方法包括从图形应用程序接收存储器请求并确定可以在处理器核心和高速缓冲存储器之间共享的高速缓存存储器是否可共享。 如果高速缓冲存储器可用于共享，则高速缓冲存储器的第一部分被分配给处理器核心，高速缓冲存储器的第二部分被分配给图形引擎。 方法和微处理器可以包括在计算设备中。

    Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains
    10.
    发明授权
    Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains 有权
    可动态配置的时钟方案，用于与多个时钟跨域相关的基于需求的资源共享

    公开(公告)号：US06735712B1

    公开(公告)日：2004-05-11

    申请号：US09657559

    申请日：2000-09-08

    申请人： Subramaniam Maiyuran ,  Lokpraveen B. Mosur ,  Salvador Palanca

    发明人： Subramaniam Maiyuran ,  Lokpraveen B. Mosur ,  Salvador Palanca

    IPC分类号： G06F104

    CPC分类号： G06F1/08 ,  G06F1/04

    摘要： A first clock signal having a first frequency is applied to drive a first module. A second clock signal having a second frequency is applied to drive a second module. The second frequency is different from the first frequency. A third clock signal is selectively applied with a frequency substantially the same as the first frequency to drive at least one portion of a resource to allow the first module to access the one portion of the resource. The third clock signal is selectively applied with a frequency substantially the same as the second frequency to drive at least the one portion of the resource to allow the second module to access the one portion of the resource.

    摘要翻译： 施加具有第一频率的第一时钟信号以驱动第一模块。 施加具有第二频率的第二时钟信号以驱动第二模块。 第二频率与第一频率不同。 选择性地以与第一频率基本相同的频率施加第三时钟信号以驱动资源的至少一部分以允许第一模块访问资源的一部分。 选择性地以与第二频率基本相同的频率施加第三时钟信号以驱动资源的至少一部分以允许第二模块访问资源的一部分。