公开(公告)号：US07487475B1

公开(公告)日：2009-02-03

申请号：US11159990

申请日：2005-06-22

申请人： Harish Kriplani ,  Shiang-Tang Huang

发明人： Harish Kriplani ,  Shiang-Tang Huang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

摘要翻译： 已经公开了执行统计静态时序分析的方法和装置。 在一个实施例中，该方法包括使用静态时序分析模块在两个或多个处理角上对多个库中的电路的性能数据进行统计分析，并且基于 在电路的自动设计流程期间的统计分析，而不使用在预定置信水平的库。

公开(公告)号：US08645881B1

公开(公告)日：2014-02-04

申请号：US13403978

申请日：2012-02-23

申请人： Harish Kriplani ,  Shiang-Tang Huang

发明人： Harish Kriplani ,  Shiang-Tang Huang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

摘要翻译： 已经公开了执行统计静态时序分析的方法和装置。 在一个实施例中，该方法包括使用静态时序分析模块在两个或多个处理角上对多个库中的电路的性能数据进行统计分析，并且基于 在电路的自动设计流程期间的统计分析，而不使用在预定置信水平的库。

公开(公告)号：US08448104B1

公开(公告)日：2013-05-21

申请号：US12345686

申请日：2008-12-30

申请人： Harish Kriplani ,  Shiang-Tang Huang

发明人： Harish Kriplani ,  Shiang-Tang Huang

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F2217/10

摘要： A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.

摘要翻译： 已经公开了执行统计静态时序分析的方法和装置。 在一个实施例中，该方法包括使用静态时序分析模块在两个或多个处理角上对多个库中的电路的性能数据进行统计分析，并且基于 在电路的自动设计流程期间的统计分析，而不使用在预定置信水平的库。

公开(公告)号：US06928630B2

公开(公告)日：2005-08-09

申请号：US10313774

申请日：2002-12-06

申请人： Cho Woo Moon ,  Harish Kriplani ,  Krishna Prasad Belkhale

发明人： Cho Woo Moon ,  Harish Kriplani ,  Krishna Prasad Belkhale

IPC分类号： G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031 ,  G06F2217/66

摘要： Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.

摘要翻译： 公开了一种用于提取定时模型的方法和系统。 一种公开的提取定时模型的方法是通过减少时序图。 原始定时行为保留在定时模型中，包括到达时间，转换时间，定时违反，甚至与时钟波形无关的锁存时间借用。 此外，原始时序约束可以在模型中捕获，并在使用模型时自动应用。 自动识别和保留锚点以获得小于原始网表的模型。

公开(公告)号：US06622290B1

公开(公告)日：2003-09-16

申请号：US09678150

申请日：2000-10-03

申请人： Arnold Ginetti ,  Mark Steven Hahn ,  Harish Kriplani ,  Naser Awad

发明人： Arnold Ginetti ,  Mark Steven Hahn ,  Harish Kriplani ,  Naser Awad

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A method for timing verification of very large scale integrated circuits reduces required CPU speed and memory usage. The method involves steps including partitioning the circuit into a plurality of blocks and then partitioning the verification between shell path components and core path components. Timing verification is then conducted for only shell path components while core path components are abstracted or ignored. Finally, timing verification for core path components in each block completes the process for the entire design.

摘要翻译： 用于定时验证超大规模集成电路的方法降低了所需的CPU速度和内存使用。 该方法包括步骤，包括将电路划分成多个块，然后在壳路径组件和核心路径组件之间划分验证。 然后，对核心路径组件进行抽象或忽略时，仅对shell路径组件进行定时验证。 最后，每个块中的核心路径组件的定时验证完成了整个设计的过程。

公开(公告)号：US07418684B1

公开(公告)日：2008-08-26

申请号：US10841000

申请日：2004-05-07

申请人： Cho W. Moon ,  Harish Kriplani

发明人： Cho W. Moon ,  Harish Kriplani

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and an apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks have been disclosed. In one embodiment, the method includes determining a plurality of sensitization conditions associated with one or more clock signals in a circuit network operable in a plurality of modes and automatically eliminating false paths from a plurality of clock paths of the circuit network based on the plurality of sensitization conditions. Other embodiments have been claimed and described.

摘要翻译： 已经公开了对多模时钟电路网络执行静态时序分析和优化的方法和装置。 在一个实施例中，该方法包括确定与在多个模式中可操作的电路网络中的一个或多个时钟信号相关联的多个敏化条件，并且基于多个模式自动消除来自电路网络的多个时钟路径的错误路径 致敏条件。 已经要求和描述了其它实施例。

公开(公告)号：US07356451B2

公开(公告)日：2008-04-08

申请号：US10313247

申请日：2002-12-06

申请人： Cho Woo Moon ,  Harish Kriplani ,  Krishna Prasad Belkhale

发明人： Cho Woo Moon ,  Harish Kriplani ,  Krishna Prasad Belkhale

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031 ,  G06F2217/66

摘要： Disclosed is a method and system for handling timing constraints or assertions for timing model extraction. One disclosed approach for assertion handling is by automatically preserving the integrity of original assertions by retaining existing pins or creating new internal pins. The assertions are viewed as part of the model, and a set of new assertions are generated automatically as part of the timing model extraction process and can be stored as part of the model. Assertions can be associated with input ports, output ports, internal pins, or hierarchical pins and can even span multiple blocks. This disclosed approach allows for application of assertions associated with timing models when the model is instantiated and detachment of assertions when the model is de-instantiated, and thus removes one of main problems associated with timing models.

摘要翻译： 公开了一种用于处理时序模型提取的时序约束或断言的方法和系统。 用于断言处理的一种公开方法是通过保留现有引脚或创建新的内部引脚来自动保持原始断言的完整性。 断言被视为模型的一部分，并且一组新的断言是自动生成的，作为时间模型提取过程的一部分，可以作为模型的一部分进行存储。 断言可以与输入端口，输出端口，内部引脚或分层引脚相关联，甚至可以跨多个块。 当模型被实例化时，该公开的方法允许应用与定时模型相关联的断言，并且在模型被去实例化时允许断言断开，并因此去除与定时模型相关联的主要问题之一。