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1.发明授权Methods and apparatuses for evaluation of regular expressions of arbitrary size 失效用于评估任意大小的正则表达式的方法和装置公开(公告)号：US07085918B2
公开(公告)日：2006-08-01
申请号：US10755048
申请日：2004-01-08
CPC分类号： G06F7/00 , G06F17/30985
摘要： Embodiments of the invention provide a programmable FSA building block, having a number of programmable registers and associated logic implemented therein, that provide the capability of contextually evaluating complex REs of arbitrary size against multiple data streams. Embodiments of the invention provide fully programmable hardware in which all of the states of an RE are instantiated and all of the states are fully connected. For one embodiment, the building blocks have a fixed number of states to facilitate implementation on a chip. For such an embodiment, an RE having an excessive number of states is implemented on two or more FSA building blocks and the FSA building blocks are then stitched together to effect evaluation of the RE. For one embodiment, two or more REs having a number of states less than the fixed number of states of a building block may be implemented with a single building block.
摘要翻译： 本发明的实施例提供了一种可编程FSA构建块，其具有在其中实现的多个可编程寄存器和相关联的逻辑，其提供对多个数据流进行任意大小的复杂RE的上下文评估的能力。 本发明的实施例提供了完全可编程硬件，其中RE的所有状态都被实例化，并且所有状态都完全连接。 对于一个实施例，构建块具有固定数量的状态以便于在芯片上实现。 对于这样的实施例，在两个或更多个FSA构建块上实现具有过多状态的RE，然后将FSA构建块缝合在一起以实现RE的评估。 对于一个实施例，具有小于构建块的固定状态数量的状态数量的两个或更多个RE可以用单个构建块来实现。
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2.发明授权Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data 有权将专用搜索寄存器和专用状态机寄存器与相关执行硬件集成在一起的可编程处理器设备支持快速应用规则集到数据公开(公告)号：US07464254B2
公开(公告)日：2008-12-09
申请号：US10755188
申请日：2004-01-08
IPC分类号： G06F7/00
CPC分类号： G06F17/30982 , G06F7/00 , G06F17/30985
摘要： A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a decoder coupled to the general purpose register file to decode a set of instructions specified by the instruction sequencer, and a state machine unit coupled to the decoder and having state machine registers to store one or more state machines and state machine execution hardware coupled to the state machine registers to evaluate the one or more state machines in response to executing one or more of the set of instructions and based on information from one or both of the decoder and the general purpose register file.
摘要翻译： 公开了一种规则处理器及其使用方法。 在一个实施例中，规则处理器包括通用寄存器文件，提供指令的指令定序器，耦合到通用寄存器文件的解码器，以对由指令定序器指定的一组指令进行解码;以及状态机单元， 解码器，并且具有状态机寄存器，用于存储耦合到状态机寄存器的一个或多个状态机和状态机执行硬件，以响应于执行该组指令中的一个或多个并且基于来自一个指令的信息来评估一个或多个状态机 或解码器和通用寄存器文件两者。
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