公开(公告)号：US07279950B2

公开(公告)日：2007-10-09

申请号：US11235758

申请日：2005-09-27

申请人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Samuel T. Ray ,  Wayne A. Utter

发明人： Hayden C. Cranford, Jr. ,  Stacy J. Garvin ,  Vernon R. Norman ,  Samuel T. Ray ,  Wayne A. Utter

IPC分类号： H03K3/00

CPC分类号： G06F1/04

摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.