公开(公告)号：US09983932B2

公开(公告)日：2018-05-29

申请号：US12982201

申请日：2010-12-30

申请人： Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

发明人： Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

IPC分类号： G06F9/38 ,  G06F11/14

CPC分类号： G06F11/1407 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867

摘要： A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

公开(公告)号：US20110296143A1

公开(公告)日：2011-12-01

申请号：US12982201

申请日：2010-12-30

申请人： Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

发明人： Heejun Shim ,  Yenjo Han ,  Jae-Young Kim ,  Yeon-Gon Cho ,  Jinseok Lee

IPC分类号： G06F9/38

CPC分类号： G06F11/1407 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867

摘要： A pipeline processor which meets a latency restriction on an equal model is provided. The pipeline processor includes a pipeline processing unit to process an instruction at a plurality of stages and an equal model compensator to store the results of the processing of some or all of the instructions located in the pipeline processing unit and to write the results of the processing in a register file based on the latency of each instruction.

摘要翻译： 提供了一种满足相等模型的等待时间限制的流水线处理器。 流水线处理器包括处理多级指令的流水线处理单元和相等模型补偿器，以存储位于流水线处理单元中的部分或全部指令的处理结果，并写入处理结果 基于每个指令的延迟，在一个寄存器文件中。