公开(公告)号：US09448283B2

公开(公告)日：2016-09-20

申请号：US14421889

申请日：2012-08-22

申请人： Heiko Ahrens ,  Claudia Latzel ,  Bernhard Richter

发明人： Heiko Ahrens ,  Claudia Latzel ,  Bernhard Richter

IPC分类号： G01R31/28 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3187

CPC分类号： G01R31/3177 ,  G01R31/318547 ,  G01R31/318575 ,  G01R31/3187

摘要： A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

摘要翻译： 用于逻辑内置自检（LBIST）的电路装置包括被配置为产生系统时钟的时钟源，被配置为导出第一冲出时钟的第一时钟分频电路和可在第一冲压时操作的多个扫描链 - 时钟。 每个扫描链具有响应于第一冲出时钟的前沿的相关联的输出电路。 电路装置包括被配置为导出第二冲出时钟的第二时钟分频电路。 第二冲出时钟相对于第一冲出时钟具有一个或多个系统时钟周期的延迟。 压缩逻辑被配置为压缩从扫描链接收的信号。 连续重新定时元件将压实逻辑连接到MISR的输入电路。 顺序重新定时元件响应于第二冲出时钟的后沿。 输入电路响应于第二冲出时钟的前沿。

公开(公告)号：US20150219717A1

公开(公告)日：2015-08-06

申请号：US14421889

申请日：2012-08-22

申请人： Heiko Ahrens ,  Claudia Latzel ,  Bernhard Richter

发明人： Heiko Ahrens ,  Claudia Latzel ,  Bernhard Richter

IPC分类号： G01R31/3177 ,  G01R31/3187

CPC分类号： G01R31/3177 ,  G01R31/318547 ,  G01R31/318575 ,  G01R31/3187

摘要： A circuit arrangement for Logic Built-In Self-Test (LBIST) includes a clock source configured to generate a system clock, a first clock division circuitry configured to derive a first punched-out clock and a plurality of scan chains operable at the first punched-out clock. Each scan chain has an associated output circuitry responsive to a leading edge of the first punched-out clock. The circuit arrangement includes a second clock division circuitry configured to derive a second punched-out clock. The second punched-out clock has a delay of one or more system clock periods relative to the first punched-out clock. A compacting logic is configured to compact signals received from the scan chains. A sequential retiming element connects the compacting logic to an input circuitry of a MISR. The sequential retiming element is responsive to a trailing edge of the second punched-out clock. The input circuitry is responsive to a leading edge of the second punched-out clock.

摘要翻译： 用于逻辑内置自检（LBIST）的电路装置包括被配置为产生系统时钟的时钟源，被配置为导出第一冲出时钟的第一时钟分频电路和可在第一冲压时操作的多个扫描链 - 时钟。 每个扫描链具有响应于第一冲出时钟的前沿的相关联的输出电路。 电路装置包括被配置为导出第二冲出时钟的第二时钟分频电路。 第二冲出时钟相对于第一冲出时钟具有一个或多个系统时钟周期的延迟。 压缩逻辑被配置为压缩从扫描链接收的信号。 连续重新定时元件将压实逻辑连接到MISR的输入电路。 顺序重新定时元件响应于第二冲出时钟的后沿。 输入电路响应于第二冲出时钟的前沿。