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公开(公告)号:US5216746A
公开(公告)日:1993-06-01
申请号:US486647
申请日:1990-02-28
申请人: Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人: Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
IPC分类号: G06N3/04
CPC分类号: G06N3/04
摘要: An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.
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公开(公告)号:US5142666A
公开(公告)日:1992-08-25
申请号:US486644
申请日:1990-02-28
申请人: Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
发明人: Hideki Yoshizawa , Hiroki Iciki , Hideki Kato , Kazuo Asakawa , Yoshihide Sugiura , Hiroyuki Tsuzuki , Hideichi Endoh , Takashi Kawasaki , Toshiharu Matsuda , Hiromu Iwamoto , Chikara Tsuchiya , Katsuya Ishikawa
CPC分类号: G06N3/04
摘要: A learning system in a neuron computer includes a neural network for receiving an analog signal from a first analog bus through an analog input port in a time divisional manner and performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. A control pattern memory stores a pattern of a signal for controlling the neural network. A sequencer produces an address of the control pattern memory and a weight memory. The weight memory stores weight data of the neural network. A digital control unit controls the neural network, control pattern memory, sequencer, and weight memory, and executes a learning algorithm. The learning system further includes an input control unit provided on the input side of the neural network for selecting an input signal for executing the learning algorithm input from the digital control unit or an analog input signal input from the analog input port.
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