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    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US4791474A

    公开(公告)日：1988-12-13

    申请号：US131323

    申请日：1987-12-08

    申请人： Yoshihide Sugiura ,  Hiroaki Ichikawa ,  Nobutake Matsumura ,  Nobuo Sasaki

    发明人： Yoshihide Sugiura ,  Hiroaki Ichikawa ,  Nobutake Matsumura ,  Nobuo Sasaki

    IPC分类号： H01L27/092 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/525 ,  H01L23/535 ,  H01L27/118 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/04

    CPC分类号： H01L27/11807 ,  H01L23/525 ,  H01L23/535 ,  H01L2924/0002

    摘要： A semiconductor integrated circuit device includes basic semiconductor elements arranged regularly in lines and rows and located at intersecting points of the lines and rows and wiring conductor layers arranged among the basic semiconductor elements regularly in lines and rows. In this semiconductor integrated circuit device, according to a desired logic operation, wiring conductor layers are cut or contact holes are formed on the wiring conductor layers to form wiring metal layers and connect the basic semiconductor elements to one another, so that an integrated circuit chip capable of performing the desired logic operation is obtained.

    摘要翻译： 半导体集成电路器件包括以行和行规则排列并且以行和行规则地布置在基本半导体元件中的线和行的交叉点和布线导体层之间的基本半导体元件。 在该半导体集成电路器件中，根据期望的逻辑运算，切断布线导体层，或者在布线导体层上形成接触孔，形成配线用金属层，并将基底半导体元件彼此连接，使集成电路芯片 能够实现所需的逻辑运算。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4412237A

    公开(公告)日：1983-10-25

    申请号：US143472

    申请日：1980-08-29

    申请人： Nobutake Matsumura ,  Ryusuke Hoshikawa ,  Yoshihide Sugiura ,  Hiroaki Ichikawa ,  Syoji Sato

    发明人： Nobutake Matsumura ,  Ryusuke Hoshikawa ,  Yoshihide Sugiura ,  Hiroaki Ichikawa ,  Syoji Sato

    IPC分类号： H01L21/822 ,  G11C5/06 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H01L29/78 ,  H03K3/356 ,  H01L27/02

    CPC分类号： H01L27/11807 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C5/063 ,  H03K3/356104 ,  Y10S257/923

    摘要： Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain. Each of the first and second single common gates has two terminal electrodes at both sides of respective basic cell array and a central terminal electrode at the center of the respective basic cell array. Further, each of the basic cells includes a small space extending between both sides of the basic cell array, which space can be utilized as a field for distributing, along a row, interconnecting lines.

    摘要翻译： PCT No.PCT / JP78 / 00048 Sec。 371日期1979年8月29日第 102（e）日期1979年8月29日PCT提交1978年12月11日PCT公布。 出版物WO79 / 00461 日期：1979年7月26日。公开是具有大量基本单元的半导体器件，其中沿着半导体衬底的行排列的多个基本单元形成基本单元阵列，并且多个基本单元阵列沿着列 并且还包括在每个相邻的柱之间形成的空间。 每个基本单元包括第一和第二P沟道MIS晶体管以及第一和第二N沟道MIS晶体管。 第一P沟道和第一N沟道MIS晶体管的栅极形成第一单个公共栅极，并且第二P沟道和第二N沟道MIS晶体管的栅极形成第二单个公共栅极。 第一P沟道和第二P沟道MIS晶体管的源极或漏极形成第一单个公共源极或漏极，并且第一N沟道和第二N沟道MIS晶体管的源极或漏极 形成第二个单一的共同来源或渠道。 第一和第二单个公共门中的每一个在各个基本单元阵列的两侧具有两个端子电极和位于各个基本单元阵列的中心的中心端子电极。 此外，每个基本单元包括在基本单元阵列的两侧之间延伸的小空间，该空间可以用作沿着一行互连线分布的场。