公开(公告)号：US20110249512A1

公开(公告)日：2011-10-13

申请号：US13080261

申请日：2011-04-05

申请人： Hikaru MOCHIZUKI ,  Yasuaki NIINO ,  Koichi MAGOME

发明人： Hikaru MOCHIZUKI ,  Yasuaki NIINO ,  Koichi MAGOME

IPC分类号： G11C7/10

CPC分类号： G11C16/32 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08

摘要： A memory chip includes: a memory region; a chip determining unit configured to perform a chip determination, in writing operation, to determine whether or not the memory region is a writing target on the basis of an inputted address of writing destination, and to output a determination result of the chip determination; an address-cycle identifying unit configured to detect a final cycle of the address of writing destination, and to output a detection result at a timing before the output of the determination result; and a buffer controller configured to switch an input buffer from one state to another on the basis of the determination result, wherein the buffer controller keeps the input buffer in an active state irrespective of the determination result of the chip determination while the address-cycle identifying unit is outputting the detection result.

摘要翻译： 存储芯片包括：存储区域; 芯片确定单元，被配置为在写入操作中执行芯片确定，以基于输入的写入目的地的地址来确定存储器区域是否是写入目标，并输出芯片确定的确定结果; 地址周期识别单元，被配置为检测写入目的地地址的最后周期，并且在确定结果的输出之前的定时输出检测结果; 以及缓冲器控制器，其被配置为基于所述确定结果将输入缓冲器从一个状态切换到另一状态，其中所述缓冲器控制器将所述输入缓冲器保持在活动状态，而与所述芯片确定的确定结果无关，而所述地址周期识别 单元正在输出检测结果。