公开(公告)号：US20100308874A1

公开(公告)日：2010-12-09

申请号：US12787687

申请日：2010-05-26

申请人： Hiroshi SEKI ,  Kiyoshi Kirino

发明人： Hiroshi SEKI ,  Kiyoshi Kirino

IPC分类号： H03K21/00

CPC分类号： H03K23/667 ,  G06F1/08

摘要： A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.

摘要翻译： 时钟切换电路包括：分频电路，其分频基本时钟的频率以产生多个分频时钟;输出选择信号产生电路，其根据时钟选择信号输出输出选择信号;以及输出选择 电路，其根据输出选择信号切换要输出的时钟，其中，分频电路从频率分配电路的每一个的一个周期的开始输出指示基本时钟的时钟数的多个分频计数值， 并且输出选择信号发生电路在开关操作之前和之后的分频时钟的开始周期的开始定时基于对应于电流的分频计数值的定时处切换输出选择信号的值 多个分频计数值中的选择时钟。

公开(公告)号：US08253449B2

公开(公告)日：2012-08-28

申请号：US12787687

申请日：2010-05-26

申请人： Hiroshi Seki ,  Kiyoshi Kirino

发明人： Hiroshi Seki ,  Kiyoshi Kirino

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： H03K23/667 ,  G06F1/08

摘要： A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.

摘要翻译： 时钟切换电路包括：分频电路，其分频基本时钟的频率以产生多个分频时钟;输出选择信号产生电路，其根据时钟选择信号输出输出选择信号;以及输出选择 电路，其根据输出选择信号切换要输出的时钟，其中，分频电路从频率分配电路的每一个的一个周期的开始输出指示基本时钟的时钟数的多个分频计数值， 并且输出选择信号发生电路在开关操作之前和之后的分频时钟的开始周期的开始定时基于对应于电流的分频计数值的定时处切换输出选择信号的值 多个分频计数值中的选择时钟。

公开(公告)号：US06266324B1

公开(公告)日：2001-07-24

申请号：US09064038

申请日：1998-04-22

申请人： Kiyoshi Kirino ,  Nobuyuki Mizukoshi ,  Hideo Ishida

发明人： Kiyoshi Kirino ,  Nobuyuki Mizukoshi ,  Hideo Ishida

IPC分类号： H04J116

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/3081 ,  H04L2012/5649 ,  H04L2012/568 ,  H04Q11/0478

摘要： In an ATM device comprising a switch core 11, a port shaping unit 25 is arranged within the switch core 11 to carry out a port shaping operation. The port shaping unit 25 controls reading timing of each cell stored in a shared buffer 10. Therefore, a delay to absorb the CDV is decided by the reading timing and the port shaping operation is achieved within the ATM device without attaching any additional memories to the ATM device.

摘要翻译： 在包括交换机核心11的ATM设备中，端口整形单元25被布置在交换机核心11内，以进行端口整形操作。 端口整形单元25控制存储在共享缓冲器10中的每个单元的读取定时。因此，吸收CDV的延迟由读取定时决定，并且在ATM设备内实现端口整形操作，而不向任何附加存储器附加 ATM设备。