公开(公告)号：US5477490A

公开(公告)日：1995-12-19

申请号：US289259

申请日：1994-08-11

申请人： Hirotomo Miyawaki ,  Noriyuki Suzuki ,  Shigeatsu Samukawa ,  Masahiro Shirai ,  Naomi Ikeda

发明人： Hirotomo Miyawaki ,  Noriyuki Suzuki ,  Shigeatsu Samukawa ,  Masahiro Shirai ,  Naomi Ikeda

IPC分类号： G06F12/02 ,  G11C7/00 ,  H04Q11/04 ,  G11C8/00

CPC分类号： G11C7/00

摘要： An elastic memory determines an amount of delay of input data relative to other input data according to a phase difference between synchronous pulses each indicating a header of a frame of the associated input data. The elastic memory thus synchronizes both input data in the channel level. Both input data are time-division multiplied by a first multiplier. On the other hand, each counter receives synchronous pulses and thereby counting up to make a ROM produce address value of which order is determined previously according to the counted value. These address values are multiplied by a second multiplier. A decoder controls a RAM, a high-impedance control unit and a flip-flop to write in and read out of the RAM the input data. The read data are divided by a signal restoring device.

摘要翻译： 弹性存储器根据同步脉冲之间的相位差确定输入数据相对于其他输入数据的延迟量，每个同步脉冲指示相关联的输入数据的帧的标题。 因此，弹性存储器使得信道级别中的两个输入数据同步。 两个输入数据都是时分乘以第一乘法器。 另一方面，每个计数器接收同步脉冲，从而向上计数，使得ROM根据计数值产生先前确定了顺序的地址值。 这些地址值乘以第二乘法器。 解码器控制RAM，高阻抗控制单元和触发器来写入和读出RAM中的输入数据。 读取的数据由信号恢复装置分割。

公开(公告)号：US07269129B2

公开(公告)日：2007-09-11

申请号：US09901197

申请日：2001-07-09

申请人： Akihiro Yasuo ,  Shigeatsu Samukawa ,  Junichi Tamura ,  Nobuyuki Umeda ,  Hiroyuki Sato ,  Tomohiro Shinomiya ,  Jun Tanaka

发明人： Akihiro Yasuo ,  Shigeatsu Samukawa ,  Junichi Tamura ,  Nobuyuki Umeda ,  Hiroyuki Sato ,  Tomohiro Shinomiya ,  Jun Tanaka

IPC分类号： G01R31/08

CPC分类号： H04J3/085 ,  H04J2203/0042 ,  H04J2203/006 ,  H04L12/437

摘要： Disclosed is a ring network in which a plurality of transmitting apparatuses are connected in ring form so as to be capable of transmitting in each of upstream and downstream directions, working and protection channels are assigned to each direction and, when failure occurs in a transmission path, a transmit signal is looped back using the protection channel to effect rescue. The ring network includes an insert transmitting apparatus that incorporates a packet, which enters from a lower-order side, into a higher-order signal and transmits the signal to a transmission path, and a drop transmitting apparatus that extracts the packet from the higher-order signal and transmits the packet to another lower-order side. Monitoring is performed to determine whether communication between the insert and drop transmitting apparatus has become unrescuable owing to transmission-path failure. When communication has become unrescuable, the insert transmitting apparatus halts the transmission of the packet to the transmission path.

摘要翻译： 公开了一种环形网络，其中多个发送装置以环形方式连接，以便能够在上游和下游方向中的每一个方向上发送，工作和保护信道被分配给每个方向，并且当在传输路径中发生故障时 ，使用保护通道循环发送信号以实现救援。 该环形网络包括：插入发送装置，其将从低级侧进入的分组并入高阶信号，并将该信号发送到传输路径;以及分组发送装置， 并将数据包发送到另一个低阶侧。 执行监视以确定插入和丢弃发送设备之间的通信是否由于传输路径故障而变得不可理解。 当通信变得不可理解时，插入发送装置将分组的传输停止到传输路径。

公开(公告)号：US06711168B1

公开(公告)日：2004-03-23

申请号：US09421466

申请日：1999-10-19

申请人： Jinichi Yoshizawa ,  Shigeatsu Samukawa

发明人： Jinichi Yoshizawa ,  Shigeatsu Samukawa

IPC分类号： H04L1228

CPC分类号： H04L12/5601 ,  H04L2012/5614 ,  H04L2012/5653 ,  H04L2012/5659

摘要： A terminating apparatus for an ATM adaptation layer is made of hardware logic circuits to terminate received cells connection by connection and assemble an ATM adaptation layer message for each connection from data contained in the received cells. The apparatus is compact and operates at high speed. The structure of the apparatus is independent of the number of connections to terminate. The apparatus has a-header extractor (4-6) for extracting a virtual path indication/virtual channel indication (VPI/VCI) from a received cell, a CRC unit (4-5) shared by cells of different connections, a reception processor (4-4) for determining whether or not the received cell is the last cell of an ATM adaptation layer message according to a payload type indication (PTI) contained in a header of the received cell and processing the received cell, a work memory (4-8) for storing, for each connection, a CRC result and the number of received cells, and a reception buffer (4-9) for sequentially storing, for each connection, data contained in cells received for the connection.

摘要翻译： 用于ATM适配层的终端设备由硬件逻辑电路构成，以通过连接终止接收到的小区连接，并从包含在所接收的小区中的数据组合用于每个连接的ATM适配层消息。 该设备结构紧凑，运行速度快。 设备的结构与要终止的连接数无关。 该装置具有从接收到的小区提取虚拟路径指示/虚拟信道指示（VPI / VCI）的头标提取器（4-6），不同连接的小区共享的CRC单元（4-5），接收处理器 （4-4），用于根据包含在所接收的小区的报头中的有效载荷类型指示（PTI）来确定所接收的小区是否是ATM适配层消息的最后一个小区，并处理接收的小区，工作存储器 4-8），用于为每个连接存储CRC结果和接收的单元的数量，以及用于为每个连接顺序地存储包含在为该连接接收的单元中的数据的接收缓冲器（4-9）。