公开(公告)号：US5241506A

公开(公告)日：1993-08-31

申请号：US612459

申请日：1990-11-14

申请人： Hiroyuki Motegi ,  Hideaki Uchida ,  Yasunori Kuwashima

发明人： Hiroyuki Motegi ,  Hideaki Uchida ,  Yasunori Kuwashima

IPC分类号： G11C11/419 ,  G11C7/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

CPC分类号： G11C7/14

摘要： A random access memory (RAM) array has a dummy word line having a similar pattern to the word lines provided for the RAM cells. A transistor having the same channel width and channel length as one of the transistors in the RAM cells has its gate connected to the dummy word line. An inverter is formed of three transistors including the transistor having its gate connected to the dummy word line, with the output of the inverter connected to a capacitor. The capacitance of the capacitor is set close to the capacitance of a bus line of the RAM to adjust the dummy word line and the word lines of the RAM circuits to have the same transfer delay. If the capacitance of the capacitor is made slightly smaller than the bus line capacitance, the potential at the output of the inverter can be changed by this difference. The output of the inverter is detected, and can be used as a drive signal to drive a sense amplifier used to read the RAM cells. Further, the signal traveling through the dummy word line can be used as a precharge signal.