公开(公告)号：US07353366B2

公开(公告)日：2008-04-01

申请号：US11277622

申请日：2006-03-28

申请人： Hiroyuki Saitoh ,  Takeshi Nishidoi

发明人： Hiroyuki Saitoh ,  Takeshi Nishidoi

IPC分类号： G06F9/00

CPC分类号： G06F11/18 ,  G06F11/3433 ,  G06F15/16 ,  G06F2201/81 ,  G06F2201/87

摘要： A transaction input/output CPU receives a transaction to be processed and outputs the execution result of the transaction. A plurality of processing CPUs execute the transaction according to an instruction from the transaction input/output CPU. A plurality of memory areas are related to each processing CPU and store a transaction which are inputted to the transaction input/output CPU and its execution result. A register stores a pointer for indicating an address common to the plurality of memory areas. The processing CPU reads a pointer from the register, and reads a transaction from the storage destination in memory corresponding to each processing CPU and executes it.

摘要翻译： 交易输入/输出CPU接收要处理的交易，并输出交易的执行结果。 多个处理CPU根据交易输入/输出CPU的指令执行交易。 多个存储区域与每个处理CPU相关，并存储输入到交易输入/输出CPU的交易及其执行结果。 寄存器存储用于指示多个存储区域共用的地址的指针。 处理CPU从寄存器读取指针，并从与每个处理CPU对应的存储器中的存储目的地读取事务并执行。

公开(公告)号：US20070174591A1

公开(公告)日：2007-07-26

申请号：US11277622

申请日：2006-03-28

申请人： Hiroyuki Saitoh ,  Takeshi Nishidoi

发明人： Hiroyuki Saitoh ,  Takeshi Nishidoi

IPC分类号： G06F11/00

CPC分类号： G06F11/18 ,  G06F11/3433 ,  G06F15/16 ,  G06F2201/81 ,  G06F2201/87

摘要： A transaction input/output CPU receives a transaction to be processed and outputs the execution result of the transaction. A plurality of processing CPUs execute the transaction according to an instruction from the transaction input/output CPU. A plurality of memory areas are related to each processing CPU and store a transaction which are inputted to the transaction input/output CPU and its execution result. A register stores a pointer for indicating an address common to the plurality of memory areas. The processing CPU reads a pointer from the register, and reads a transaction from the storage destination in memory corresponding to each processing CPU and executes it.

摘要翻译： 交易输入/输出CPU接收要处理的交易，并输出交易的执行结果。 多个处理CPU根据交易输入/输出CPU的指令执行交易。 多个存储区域与每个处理CPU相关，并存储输入到交易输入/输出CPU的交易及其执行结果。 寄存器存储用于指示多个存储区域共用的地址的指针。 处理CPU从寄存器读取指针，并从与每个处理CPU对应的存储器中的存储目的地读取事务并执行。