公开(公告)号：US07155690B2

公开(公告)日：2006-12-26

申请号：US10766955

申请日：2004-01-30

申请人： Hiroyuki Yamashita ,  Takao Shinsha ,  Hideaki Fujikake ,  Toshiaki Kowatari ,  Tomoya Hirao ,  Atsushi Ohkuma ,  Hiroaki Nishi ,  Michiaki Muraoka

发明人： Hiroyuki Yamashita ,  Takao Shinsha ,  Hideaki Fujikake ,  Toshiaki Kowatari ,  Tomoya Hirao ,  Atsushi Ohkuma ,  Hiroaki Nishi ,  Michiaki Muraoka

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5022 ,  G01R31/318314 ,  G06F2217/86

摘要： A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

摘要翻译： 一种通过实现基于C的本地代码模拟实现快速仿真执行的硬件/软件协同验证方法，而不会降低定时验证的准确性。 该方法是用于通过使用主机CPU对安装至少一个目标CPU和一个OS的半导体器件来共同验证硬件和软件的方法，其中首先，以基于C的语言描述的定时软件组件 或者由主机CPU本机的二进制代码构成，并将基于C语言描述的硬件组件输入作为验证模型，执行必要的编译，并将已编译的组件链接在一起。 接下来，输入和编译测试台。 然后，将组件和测试台连接在一起，然后进行仿真并输出仿真结果。

公开(公告)号：US20050149897A1

公开(公告)日：2005-07-07

申请号：US10766955

申请日：2004-01-30

申请人： Hiroyuki Yamashita ,  Takao Shinsha ,  Hideaki Fujikake ,  Toshiaki Kowatari ,  Tomoya Hirao ,  Atsushi Ohkuma ,  Hiroaki Nishi ,  Michiaki Muraoka

发明人： Hiroyuki Yamashita ,  Takao Shinsha ,  Hideaki Fujikake ,  Toshiaki Kowatari ,  Tomoya Hirao ,  Atsushi Ohkuma ,  Hiroaki Nishi ,  Michiaki Muraoka

IPC分类号： G06F11/28 ,  G01R31/3183 ,  G06F17/50

CPC分类号： G06F17/5022 ,  G01R31/318314 ,  G06F2217/86

摘要： A hardware/software co-verification method that achieves fast simulation execution by implementing a C-based native code simulation without degrading the accuracy of timing verification. This method is a method for co-verifying hardware and software, by using a host CPU, for a semiconductor device on which at least one target CPU and one OS are mounted wherein, first, a timed software component described in a C-based language or constructed from binary code native to the host CPU and a hardware component described in the C-based language are input as verification models, necessary compiling is performed, and the compiled components are linked together. Next, a testbench is input and compiled. Then, the components and the testbench are linked together, after which simulation is performed and the result of the simulation is output.

摘要翻译： 一种通过实现基于C的本地代码模拟实现快速仿真执行的硬件/软件协同验证方法，而不会降低定时验证的准确性。 该方法是用于通过使用主机CPU对安装至少一个目标CPU和一个OS的半导体器件来共同验证硬件和软件的方法，其中首先，以基于C的语言描述的定时软件组件 或者由主机CPU本机的二进制代码构成，并将基于C语言描述的硬件组件输入作为验证模型，执行必要的编译，并将已编译的组件链接在一起。 接下来，输入和编译测试台。 然后，将组件和测试台连接在一起，然后进行仿真并输出仿真结果。