公开(公告)号：US12124732B2

公开(公告)日：2024-10-22

申请号：US18116683

申请日：2023-03-02

Applicant: Hitachi, Ltd.

Inventor： Satoshi Kodaira ,  Yusuke Yamamoto ,  Yoshihide Shirai

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: An information processing apparatus includes a main CPU storage area and a sub-CPU storage area. The information processing apparatus further includes an FPGA capable of processing access to the main CPU storage area by a main CPU and access to the sub-CPU storage area by a second CPU in parallel. The FPGA has an FPGA control unit that performs processing. The FPGA control unit is configured to read prescribed data from an SPI device to the main CPU storage area and the sub-CPU storage area, update the prescribed data of the sub-CPU storage area when receiving an updating request from the sub-CPU, and read the prescribed data of the main CPU storage area to the main CPU when receiving a reading request from the main CPU.