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    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 有权

    公开(公告)号：US06452851B1

    公开(公告)日：2002-09-17

    申请号：US09830416

    申请日：2001-04-27

    申请人： Hitoshi Endo ,  Katsuhiko Wakasugi ,  Youichi Sato ,  Kazuyoshi Sato

    发明人： Hitoshi Endo ,  Katsuhiko Wakasugi ,  Youichi Sato ,  Kazuyoshi Sato

    IPC分类号： G11C700

    CPC分类号： G11C11/419 ,  G11C5/025

    摘要： A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

    Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier
    2.
    发明授权
    Semiconductor integrated circuit device using static memory cells with bit line pre-amplifier and main amplifier 有权
    半导体集成电路器件采用具有位线前置放大器和主放大器的静态存储单元

    公开(公告)号：US06542424B2

    公开(公告)日：2003-04-01

    申请号：US10173433

    申请日：2002-06-18

    申请人： Hitoshi Endo ,  Katsuhiko Wakasugi ,  Youichi Sato ,  Kazuyoshi Sato

    发明人： Hitoshi Endo ,  Katsuhiko Wakasugi ,  Youichi Sato ,  Kazuyoshi Sato

    IPC分类号： G11C700

    CPC分类号： G11C7/065 ,  G11C7/18 ,  G11C11/419

    摘要： A memory cell array configured using static memory cells is provided with pre-amplifiers each of which receives a signal of a memory cell, which is read into each complementary bit line pair, and a main amplifier which receives a signal outputted from each of the pre-amplifiers. The number of the plurality of memory cells connected to the complementary bit lines is restricted in such a manner that the amplitude of the signal read into each complementary bit line pair, which is supplied to the input of the pre-amplifier, becomes greater than that of a signal outputted from the pre-amplifier during a period of from the selection of a word line to the start of the operation of the main amplifier.

    摘要翻译： 使用静态存储单元配置的存储单元阵列具有预放大器，每个预放大器接收读入每个互补位线对的存储单元的信号，以及主放大器，其接收从每个前级输出的信号 放大器。 连接到互补位线的多个存储单元的数量被限制为使得被提供给前置放大器的输入的读取到每个互补位线对的信号的幅度变得大于 在从选择字线到主放大器的操作开始的时段期间从前置放大器输出的信号。