公开(公告)号：US07743233B2

公开(公告)日：2010-06-22

申请号：US11100032

申请日：2005-04-05

申请人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

发明人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

IPC分类号： G06F9/00

CPC分类号： G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

摘要： Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

摘要翻译： 公开了用于管理和转换逻辑定序器地址与多序列器多线程系统中的物理或逻辑顺控程序之间的映射的系统，方法和机制的实施例。 映射管理器可以管理逻辑顺控程序地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这样的映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US5752071A

公开(公告)日：1998-05-12

申请号：US503251

申请日：1995-07-17

申请人： Graham S. Tubbs ,  James Charles Abel

发明人： Graham S. Tubbs ,  James Charles Abel

IPC分类号： G06F9/38 ,  G06F15/16

CPC分类号： G06F9/3887 ,  G06F9/30036 ,  G06F9/3877

摘要： A function coprocessor for a processor having a first type of coprocessor interface is described. The function coprocessor includes a subprocessor and program memory coupled to the subprocessor. A data memory stores data from the processor in response to a first control signal. The data memory has m ports coupled to the subprocessor for providing up to m operands to the subprocessor per clock cycle. The function coprocessor also includes a function coprocessor interface compatible with the first type of coprocessor interface for coupling to the processor. The function coprocessor interface generates the first control signal in response to interface signals received from the coprocessor interface of the processor. The function coprocessor interface provides handshake signals to the coprocessor interface of the processor including a busy signal, an error signal, and a processor extension request signal.

摘要翻译： 描述了具有第一类协处理器接口的处理器的功能协处理器。 功能协处理器包括耦合到子处理器的子处理器和程序存储器。 数据存储器响应于第一控制信号存储来自处理器的数据。 数据存储器具有耦合到子处理器的m个端口，用于每个时钟周期向子处理器提供多达m个操作数。 功能协处理器还包括与第一类协处理器接口兼容的功能协处理器接口，用于耦合到处理器。 功能协处理器接口根据从处理器的协处理器接口接收的接口信号产生第一控制信号。 功能协处理器接口向处理器的协处理器接口提供握手信号，包括忙信号，错误信号和处理器扩展请求信号。