公开(公告)号：US06767831B1

公开(公告)日：2004-07-27

申请号：US10632380

申请日：2003-08-01

申请人： Hong-Yuan Chu ,  Chih-Jian Chen

发明人： Hong-Yuan Chu ,  Chih-Jian Chen

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/665

摘要： A method for forming salicides with reduced junction leakage including providing a semiconductor process wafer comprising a silicon substrate; inducing amorphization within the silicon substrate to a form a first amorphous region having a first predetermined depth measured from the silicon substrate surface; carrying out at least one first thermal annealing process to controllably partially recrystallize the first amorphous region to produce a second amorphous region having a second predetermined depth less than the first predetermined depth; depositing a metal layer over selected areas of the silicon substrate comprising the second amorphous region; and, carrying out at least one second thermal annealing process to form a metal silicide.

摘要翻译： 一种用于形成具有降低的结漏电的防腐剂的方法，包括提供包括硅衬底的半导体工艺晶片; 在硅衬底内引起非晶化，形成具有从硅衬底表面测量的第一预定深度的第一非晶区; 执行至少一个第一热退火工艺以可控地部分地重结晶所述第一非晶区域以产生具有小于所述第一预定深度的第二预定深度的第二非晶区域; 在包括所述第二非晶区域的所述硅衬底的选定区域上沉积金属层; 并进行至少一个第二热退火工艺以形成金属硅化物。

公开(公告)号：US20050263891A1

公开(公告)日：2005-12-01

申请号：US11100912

申请日：2005-04-07

申请人： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

发明人： Bih-Huey Lee ,  Hong-Yuan Chu ,  Ping-Kun Wu ,  Ching-Wen Lu ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Shing-Chyang Pan

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76844 ,  H01L21/76867

摘要： A damascene structure for semiconductor devices is provided. In an embodiment, the damascene structure includes trenches formed over vias that electrically couple the trenches to an underlying conductive layer such that the trenches have varying widths. The vias are lined with a first barrier layer. The first barrier layers along the bottom of vias are removed such that a recess formed in the underlying conductive layer. The recesses formed along the bottom of vias are such that the recess below narrower trenches is greater than the recess formed below wider trenches. In another embodiment, a second barrier layer may then be formed over the first barrier layer. In this embodiment, a portion of the conductive layer may be interposed between the first barrier layer and the second barrier layer.

摘要翻译： 提供了一种用于半导体器件的镶嵌结构。 在一个实施例中，镶嵌结构包括在通孔上形成的沟槽，其将沟槽电耦合到下面的导电层，使得沟槽具有变化的宽度。 通孔排列有第一阻挡层。 沿着通孔底部的第一阻挡层被去除，使得形成在下面的导电层中的凹陷。 沿着通孔底部形成的凹槽使得较窄沟槽下面的凹陷大于形成在较宽沟槽下方的凹陷。 在另一个实施例中，然后可以在第一阻挡层上形成第二阻挡层。 在该实施例中，导电层的一部分可插入在第一阻挡层和第二阻挡层之间。

公开(公告)号：US06866988B2

公开(公告)日：2005-03-15

申请号：US10264521

申请日：2002-10-05

申请人： Shyue-Sheng Lu ,  Hong-Yuan Chu ,  Kuei-Shun Chen ,  Hua-Tai Lin

发明人： Shyue-Sheng Lu ,  Hong-Yuan Chu ,  Kuei-Shun Chen ,  Hua-Tai Lin

IPC分类号： G03F7/40 ,  G03C5/00

CPC分类号： G03F7/40

摘要： A new and improved method for measuring dimensions of a photoresist pattern profile on a wafer substrate during photolithography for the fabrication of integrated circuits on the substrate. According to one embodiment, the method includes fixing the photoresist pattern profile on the substrate using a spin-on glass (SOG) procedure. In another embodiment, the method includes fixing the photoresist pattern profile on the substrate using a sputter oxide (SO) procedure. The fixed photoresist pattern is then subjected to a microscopy procedure, typically transmission electron microscopy (TEM), to measure the exact linewidth and other dimensions of the profile. The method prevents distortion of the profile during fixation and facilitates an accurate determination of the profile dimensions.

摘要翻译： 一种用于在光刻期间测量晶片衬底上的光致抗蚀剂图案轮廓的尺寸的新的和改进的方法，用于在衬底上制造集成电路。 根据一个实施例，该方法包括使用旋涂玻璃（SOG）程序将光致抗蚀剂图案轮廓固定在基底上。 在另一个实施例中，该方法包括使用溅射氧化物（SO）程序将光致抗蚀剂图案轮廓固定在基底上。 然后将固定的光致抗蚀剂图案进行显微镜程序，通常是透射电子显微镜（TEM），以测量轮廓的精确线宽和其他尺寸。 该方法可防止固定过程中的轮廓变形，并有助于精确确定轮廓尺寸。