公开(公告)号：US20080052582A1

公开(公告)日：2008-02-28

申请号：US11493784

申请日：2006-07-26

申请人： Hongshin Jun ,  Gyaneshwar S. Saharia ,  William Eklow

发明人： Hongshin Jun ,  Gyaneshwar S. Saharia ,  William Eklow

IPC分类号： G01R31/28

CPC分类号： G06F11/267

摘要： Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis system(s). JTAG commands are received and converted into commands sent out a bus to a device including an embedded analysis instrument, with results received over the bus forwarded out the JTAG interface to an external device. Such a JTAG to system bus interface may eliminate the need to provide separate JTAG TAP interfaces on each ASIC of a board, and/or eliminate the need to daisy chain multiple TAP interfaces of multiple ASICs in order to provide a single TAP interface for accessing the multiple embedded testing instruments.

摘要翻译： 公开的方法，装置，数据结构，计算机可读介质，机制和装置，用于向用于访问嵌入式分析系统的系统总线接口提供JTAG。 JTAG命令被接收并转换成发送到包括嵌入式分析仪器的设备的总线的命令，通过总线接收的结果将JTAG接口转发到外部设备。 这样的JTAG到系统总线接口可以消除在板的每个ASIC上提供单独的JTAG TAP接口的需要，和/或不需要菊花链多个ASIC的多个TAP接口，以便提供单个TAP接口来访问 多种嵌入式测试仪器。

公开(公告)号：US07543208B2

公开(公告)日：2009-06-02

申请号：US11493784

申请日：2006-07-26

申请人： Hongshin Jun ,  Gyaneshwar S. Saharia ,  William Eklow

发明人： Hongshin Jun ,  Gyaneshwar S. Saharia ,  William Eklow

IPC分类号： G01R31/28

CPC分类号： G06F11/267

摘要： Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis system(s). JTAG commands are received and converted into commands sent out a bus to a device including an embedded analysis instrument, with results received over the bus forwarded out the JTAG interface to an external device. Such a JTAG to system bus interface may eliminate the need to provide separate JTAG TAP interfaces on each ASIC of a board, and/or eliminate the need to daisy chain multiple TAP interfaces of multiple ASICs in order to provide a single TAP interface for accessing the multiple embedded testing instruments.

摘要翻译： 公开的方法，装置，数据结构，计算机可读介质，机制和装置，用于向用于访问嵌入式分析系统的系统总线接口提供JTAG。 JTAG命令被接收并转换成发送到包括嵌入式分析仪器的设备的总线的命令，通过总线接收的结果将JTAG接口转发到外部设备。 这样的JTAG到系统总线接口可以消除在板的每个ASIC上提供单独的JTAG TAP接口的需要，和/或不需要菊花链多个ASIC的多个TAP接口，以便提供单个TAP接口来访问 多种嵌入式测试仪器。

公开(公告)号：US20130318410A1

公开(公告)日：2013-11-28

申请号：US13477150

申请日：2012-05-22

申请人： Hongshin Jun ,  William Eklow ,  Sun-Gyu Kim

发明人： Hongshin Jun ,  William Eklow ,  Sun-Gyu Kim

IPC分类号： G01R31/3185 ,  G06F11/25

CPC分类号： G01R31/318547 ,  G01R31/318544

摘要： A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.

摘要翻译： 通过向耦合到与IEEE 1149.6测试接收机相关联的IEEE 1149.6边界扫描单元的串行输入引脚提供测试模式来执行组件测试的方法。 测试接收器被配置为在扫描测试模式下操作。 来自测试接收器电路的输出被耦合到待扫描测试的逻辑块。 在扫描测试模式下，逻辑块的输出与集成电路上的串行输出引脚相连。 高性能集成电路可以在扫描测试模式下使用SerDes引脚进行扫描测试，而不会影响任务关键信号。

公开(公告)号：US08935583B2

公开(公告)日：2015-01-13

申请号：US13477150

申请日：2012-05-22

申请人： Hongshin Jun ,  William Eklow ,  Sun-Gyu Kim

发明人： Hongshin Jun ,  William Eklow ,  Sun-Gyu Kim

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318544

摘要： A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.

摘要翻译： 通过向耦合到与IEEE 1149.6测试接收机相关联的IEEE 1149.6边界扫描单元的串行输入引脚提供测试模式来执行组件测试的方法。 测试接收器被配置为在扫描测试模式下操作。 来自测试接收器电路的输出被耦合到待扫描测试的逻辑块。 在扫描测试模式下，逻辑块的输出与集成电路上的串行输出引脚相连。 高性能集成电路可以在扫描测试模式下使用SerDes引脚进行扫描测试，而不会影响任务关键信号。

公开(公告)号：US07089470B1

公开(公告)日：2006-08-08

申请号：US10412192

申请日：2003-04-11

申请人： Sang Hyeon Baeg ,  Sung Soo Chung ,  Hongshin Jun

发明人： Sang Hyeon Baeg ,  Sung Soo Chung ,  Hongshin Jun

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31855 ,  G01R31/318577

摘要： Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.

摘要翻译： 用于边界扫描集群或功能块测试的可编程测试模式驱动程序和捕获机制。 边界扫描测试系统包括至少一个被测设备。 该设备可以包括测试接入端口（TAP）控制器，多个输出AC边界扫描小区（BSC）和多个输入AC BSC。 该设备还可以包括可编程AC_Pattern_Source信号发生器，其被配置为产生在原始捕获周期位置之前和之后选择性地保持不变的AC信号模式，可编程AC_Sync信号发生器被配置为独立地控制AC_Sync信号导致或滞后 以全周期增量的原始周期位置，被配置为独立地控制上升沿或下降沿对齐的AC_Pattern_Clock信号或AC_Counter_Clock信号的可编程相位控制器，以及AC_Test_Clock信号切换器，其被配置为选择性地利用多个时钟信号中的一个，包括TCK信号 。