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公开(公告)号:US20100102875A1
公开(公告)日:2010-04-29
申请号:US12578569
申请日:2009-10-13
申请人: Hongwei Zhao , Jian Yang , Iven Zheng , Tommy Mao , Waley Li
发明人: Hongwei Zhao , Jian Yang , Iven Zheng , Tommy Mao , Waley Li
CPC分类号: H01L27/0207 , H01L27/0623
摘要: A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.
摘要翻译: 用于降压转换器的基板噪声的被动消除方法使用片上电容器来降低衬底噪声。 电容器实现了具有相反相位的近似噪声,从而在衬底中获得更好的噪声消除效果。 电容器可以实现为MOS电容器,NMOS隔离环n阱电容器,n阱结电容器,隔离p阱结电容器等。电容器易于实现。 此外,降压转换器中的接合线寄生电感用于降低基板噪声。
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公开(公告)号:US08179187B2
公开(公告)日:2012-05-15
申请号:US12578569
申请日:2009-10-13
申请人: Hongwei Zhao , Jian Yang , Iven Zheng , Tommy Mao , Waley Li
发明人: Hongwei Zhao , Jian Yang , Iven Zheng , Tommy Mao , Waley Li
IPC分类号: H03K17/16
CPC分类号: H01L27/0207 , H01L27/0623
摘要: A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.
摘要翻译: 用于降压转换器的基板噪声的被动消除方法使用片上电容器来减少衬底噪声。 电容器实现了具有相反相位的近似噪声,从而在衬底中获得更好的噪声消除效果。 电容器可以实现为MOS电容器,NMOS隔离环n阱电容器,n阱结电容器,隔离p阱结电容器等。电容器易于实现。 此外,降压转换器中的接合线寄生电感用于降低基板噪声。
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公开(公告)号:US07940092B2
公开(公告)日:2011-05-10
申请号:US12554995
申请日:2009-09-08
申请人: Iven Zheng , Waley Li , Linpeng Wei , Hongwei Zhao , Weiying Li
发明人: Iven Zheng , Waley Li , Linpeng Wei , Hongwei Zhao , Weiying Li
IPC分类号: H03K3/00
CPC分类号: H03K17/08122 , H02M7/538
摘要: An H bridge circuit includes a gate driver circuit coupled to a gate of an NMOS device. The output of the gate driver circuit is at a voltage from 0.1V to 0.4V during a dead time of the H bridge circuit. The gate voltage of the NMOS device is biased at 0.1˜0.4V to overcome the problems of minority carrier injection and power dissipation as compared with VG=0 in a conventional H bridge circuit.
摘要翻译: H桥电路包括耦合到NMOS器件的栅极的栅极驱动器电路。 在H桥电路的死区时间内,栅极驱动电路的输出为0.1V至0.4V的电压。 在常规H桥电路中,NMOS器件的栅极电压偏置在0.1〜0.4V,以克服少量载流子注入和功耗的问题,与VG = 0相比。
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