-
1.发明申请SUPPRESSION OF HOT-CARRIER EFFECTS USING DOUBLE WELL FOR THIN GATE OXIDE LDMOS EMBEDDED IN HV PROCESS 有权在高压工艺中嵌入薄壁氧化物LDMOS的双载体效应的抑制公开(公告)号：US20070267693A1
公开(公告)日：2007-11-22
申请号：US11419685
申请日：2006-05-22
申请人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
发明人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42364 , H01L29/7816
摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
摘要翻译： 半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。
-
2.发明授权Suppression of hot-carrier effects using double well for thin gate oxide LDMOS embedded in HV process 有权使用双阱抑制热载流子效应，用于嵌入HV工艺的薄栅极氧化物LDMOS公开(公告)号：US08004038B2
公开(公告)日：2011-08-23
申请号：US11419685
申请日：2006-05-22
申请人： Hsing-Yi Chien , Yu-Chang Jong , Te-Yin Hsia , Ruey-Shin Liu
发明人： Hsing-Yi Chien , Yu-Chang Jong , Te-Yin Hsia , Ruey-Shin Liu
IPC分类号： H01L31/062
CPC分类号： H01L29/7835 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42364 , H01L29/7816
摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
摘要翻译： 半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。
-
搜索结果
2 条记录 (耗时 0.191 秒)
