公开(公告)号：US20190123308A1

公开(公告)日：2019-04-25

申请号：US16011645

申请日：2018-06-19

申请人： Hua ZHENG ,  Lei YANG ,  Wei ZHANG ,  Lixian FAN ,  Geng ZHANG ,  Shaoqiang ZHANG ,  Minxia LIU ,  Chunhua LI

发明人： Hua ZHENG ,  Lei YANG ,  Wei ZHANG ,  Lixian FAN ,  Geng ZHANG ,  Shaoqiang ZHANG ,  Minxia LIU ,  Chunhua LI

IPC分类号： H01L51/56 ,  H01L51/50 ,  H01L51/52 ,  H01L51/00

CPC分类号： H01L51/56 ,  H01L27/3246 ,  H01L27/3283 ,  H01L51/0005 ,  H01L51/5056 ,  H01L51/5072 ,  H01L51/5092 ,  H01L51/5096 ,  H01L51/5206 ,  H01L51/5221

摘要： The invention discloses a preparation method for a printing OLED display, comprising the following steps: preparing a hole injection layer, a hole transfer layer or an electron blocking layer on an anodic substrate; forming a soluble fluorine-containing insulation layer with a printing method to encapsulate the whole substrate; performing inkjet printing on the soluble fluorine-containing insulation layer with a fluorine solvent to wash to expose all sub-pixel pits; performing inkjet printing with the solution drops of luminescent materials to form a RGB luminescent layer in the sub-pixel pits; preparing an electron injection layer, an electron transfer layer or a hole blocking layer; preparing a cathode with a printing method or an evaporating method, and finally performing encapsulation to complete the preparation of the single printing OLED display.

公开(公告)号：US20090146258A1

公开(公告)日：2009-06-11

申请号：US12368283

申请日：2009-02-09

申请人： Shaoqiang ZHANG ,  Purakh Raj VERMA ,  Sanford CHU

发明人： Shaoqiang ZHANG ,  Purakh Raj VERMA ,  Sanford CHU

IPC分类号： H01L29/72 ,  H01L21/8238 ,  H01L21/8249

CPC分类号： H01L21/82285 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/7378

摘要： A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained different types of impurity profile, they need separate lithography and doping step for each transistor. The process is easy to integrate with existing CMOS process to save manufacturing time and cost. As plug-in module, fully integration with SiGe BiCMOS processes. High doping Polysilicon Emitter can increase hole injection efficiency from emitter to base, reduce emitter resistor, and form very shallow EB junction. Self-aligned N+ base implant can reduce base resistor and parasitical EB capacitor. Very low collector resistor benefits from BP layer. PNP transistor can be Isolated from other CMOS and NPN devices by BNwell, Nwell and BN+ junction.

摘要翻译： 用于高性能SiGe CBiCMOS工艺的自对准垂直PNP晶体管的结构和工艺。 实施例包括具有高性能SiGe NPN晶体管和PNP晶体管的SiGe CBiCMOS。 由于PNP晶体管和NPN晶体管包含不同类型的杂质分布，因此每个晶体管需要单独的光刻和掺杂步骤。 该过程易于与现有的CMOS工艺集成，以节省制造时间和成本。 作为插件模块，与SiGe BiCMOS工艺完全集成。 高掺杂多晶硅发射器可以增加从发射极到基极的空穴注入效率，减少发射极电阻，并形成非常浅的EB结。 自对准N +基极植入可以减少基极电阻和寄生EB电容。 极低的集电极电阻受益于BP层。 PNP晶体管可以通过BNwell，Nwell和BN +结与其他CMOS和NPN器件隔离。