公开(公告)号：US10733101B2

公开(公告)日：2020-08-04

申请号：US16047892

申请日：2018-07-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hao Xiao ,  Yuangang Wang ,  Jun Xu

IPC: G06F12/0815 ,  G06F9/46 ,  G06F9/52 ,  G06F12/0806 ,  G06F12/0831

Abstract: A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.

公开(公告)号：US20180373634A1

公开(公告)日：2018-12-27

申请号：US16047892

申请日：2018-07-27

Applicant: Huawei Technologies Co., Ltd.

Inventor： Hao Xiao ,  Yuangang Wang ,  Jun Xu

IPC: G06F12/0815 ,  G06F9/46

Abstract: A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.