公开(公告)号：US20240330202A1

公开(公告)日：2024-10-03

申请号：US18673967

申请日：2024-05-24

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Pan ,  Junping Luo ,  Tao Li ,  Kenneth Chong Yin Tan ,  Junlong Liu

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/657

Abstract: A plurality of physical cores of a processor share a memory management unit (MMU) pool comprising a plurality of MMUs. The plurality of MMUs provides each physical core with an address translation function from a virtual address (VA) to a physical address (PA). If an address translation requirement of a physical core is high, for example, when a main memory is concurrently accessed, the plurality of MMUs can serve the physical core.

公开(公告)号：US20240403224A1

公开(公告)日：2024-12-05

申请号：US18807043

申请日：2024-08-16

Applicant: Huawei Technologies Co., Ltd.

Inventor： Wei Pan ,  Junping Luo ,  Tao Li ,  Kenneth Chong Yin Tan ,  Junlong Liu

IPC: G06F12/1009

Abstract: A memory access method comprises adding routing information to a memory page table, so that a memory management unit (MMU) queries, in a process of performing address translation on a virtual address (VA), the memory page table to obtain the routing information. After querying the memory page table and obtaining a physical address (PA), the MMU may directly route the PA based on the routing information, whereby a system address decoder (SAD) is not needed for further decoding the PA.