公开(公告)号：US20190034271A1

公开(公告)日：2019-01-31

申请号：US16148478

申请日：2018-10-01

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shengbin Zhang ,  Qiang Lin ,  Yifeng Yang

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: A data processing apparatus, including data dies, an error checking and correcting (ECC) die, a double data rate synchronous dynamic random access memory (RAM) (DDR) controller, and a DDR physical interface (PHY). The data dies and the ECC die are DDR dies of a same data bit width, and the DDR PHY is coupled to data interfaces of the data dies and the ECC die. The DDR controller includes a first checking circuit, a second checking circuit, and a cache. Both of the two checking circuits are coupled to the cache, type 1 interfaces of the two checking circuits are coupled to the data interfaces of the data dies using the DDR PHY, and type 2 interfaces of the two checking circuits are coupled to the data interface of the ECC die using the DDR PHY.