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公开(公告)号：US20210103002A1
公开(公告)日：2021-04-08
申请号：US17126895
申请日：2020-12-18
Applicant: Huawei Technologies Co., Ltd.
Inventor： Juan Li , Hui Li , Tuanbao Fan , Yangxing Li
IPC: G01R31/3842 , G01R31/389
Abstract: A method and apparatus include obtaining, during a preconfigured time interval, a current-moment charge/discharge current, a current-moment temperature, a current-moment coulomb capacity, and a previous-moment state of charge (SOC) value of a battery, obtaining a discharge duration of the battery, determining a current-moment internal resistance response type of the battery based on the discharge duration, determining current-moment internal resistance data of the battery based on the current-moment internal resistance response type, the current-moment temperature, the current-moment charge/discharge current, and the previous-moment SOC value, determining a current-moment unusable capacity of the battery based on the current-moment internal resistance data, the current-moment charge/discharge current, and the current-moment temperature, and determining a current-moment SOC value of the battery based on the current-moment coulomb capacity and the current-moment unusable capacity.
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公开(公告)号：US11855661B2
公开(公告)日：2023-12-26
申请号：US17750299
申请日：2022-05-21
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Yuexing Jiang , Xiaoshan Shi , Rongjun Wang
CPC classification number: H03M7/3066 , G06F7/50 , G06F7/523 , H03M7/6011
Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.
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Patent Agency Ranking
公开(公告)号：US20220294468A1
公开(公告)日：2022-09-15
申请号：US17750299
申请日：2022-05-21
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Yuexing Jiang , Xiaoshan Shi , Rongjun Wang
Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.
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公开(公告)号：US12170479B2
公开(公告)日：2024-12-17
申请号：US17951469
申请日：2022-09-23
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Ningbo Sun , Xiaoshan Shi , Yi Wang
Abstract: A power management system includes a direct current-direct current DC-DC conversion circuit, a first control circuit, a charging circuit, an input port, and an output port. The input port is configured to receive an input voltage. The output port is configured to supply an output voltage to a load. The DC-DC conversion circuit is configured to charge the output port from the input port, to adjust the output voltage. The first control circuit is configured to: obtain a second feedback voltage of the output voltage from the output port, generate a first control signal based on the second feedback voltage and a second reference signal, and supply the first control signal to the charging circuit. The charging circuit charges the output port from the input port based on the first control signal, to supplementally adjust the output voltage.
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公开(公告)号：US20240168714A1
公开(公告)日：2024-05-23
申请号：US18424893
申请日：2024-01-29
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Xiaoshan Shi , Yuexing Jiang , Mingfeng Jiang
CPC classification number: G06F7/5318 , G06F7/50
Abstract: This application provides an accumulator, a multiplier, and an operator circuit, and relates to the field of electronic technologies, to reduce an area and power consumption of the accumulator. The accumulator includes W compressor layers, where W is an integer greater than or equal to 1. The W compressor layers include at least one first compressor layer. In an input array of each first compressor layer, a first array includes a plurality of positive-phase bits, and a second array includes a plurality of negative-phase bits. Each first compressor layer includes a first compression circuit configured to compress the first array and a second compression circuit configured to compress the second array. To be specific, bits with different phases in the input array of each first compressor layer are compressed by different compression circuits.
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公开(公告)号：US20240427406A1
公开(公告)日：2024-12-26
申请号：US18824694
申请日：2024-09-04
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Eitan Rosen , Ningbo Sun , Yang Wang , Xiaoshan Shi , Mingfeng Jiang , Yu Liu , Zhangrong Hu
Abstract: A power supply circuit and a frequency adjustment method are provided, to improve running stability of a processing module (200). The power supply circuit obtains an operating voltage of the processing module (200), and generates, based on the operating voltage, a clock signal that indicates an operating frequency of the processing module (200), so that the processing module (200) runs at an operating frequency corresponding to a current operating voltage. Even if the operating voltage fluctuates, running of the processing module (200) is not affected. This improves running stability of the processing module (200) without increasing power consumption.
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公开(公告)号：US20240168715A1
公开(公告)日：2024-05-23
申请号：US18430566
申请日：2024-02-01
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tuanbao Fan , Xiaoshan Shi , Yuexing Jiang , Mingfeng Jiang
Abstract: A multiplier implements multiplication of a first value and a second value, and includes P precoders, P encoder groups, and a compressor, where each precoder is configured to: precode at least two bits in the second value, to output a selection signal group; each encoder group is configured to: encode the first value and a selection signal group output by a precoder corresponding to the encoder group, to output a partial product item; the P encoder groups include a first encoder group, a first encoder of the first encoder group is configured to: encode a first selection signal group, a least significant bit in the first value, and a first sign bit, to obtain a first partial product and a first output sign bit, the first selection signal group is a selection signal group output by a first precoder, and the first precoder corresponds to the first encoder group.
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