公开(公告)号：US11907122B2

公开(公告)日：2024-02-20

申请号：US17886718

申请日：2022-08-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuejian Xie ,  Qian Wang ,  Xingyu Jiang

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: The disclosure relates to technology for up-evicting cache lines. An apparatus comprises a hierarchy of caches comprising a first cache having a first cache controller and a second cache having a second cache controller. The first cache controller is configured to store cache lines evicted from a first processor group to the first cache and to down-evict cache lines from the first cache to the second cache. The second cache controller is configured to store cache lines evicted from a second processor group into the second cache, to up-evict a first cache line from the second cache to the first cache in response to an eviction of a second cache line from the second processor group to the second cache, and to provide the up-evicted first cache line from the first cache to the second processor group in response to a request from the second processor group.

公开(公告)号：US12298906B2

公开(公告)日：2025-05-13

申请号：US17902263

申请日：2022-09-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuejian Xie ,  Qian Wang ,  Xingyu Jiang

IPC: G06F12/0811 ,  G06F12/1009

Abstract: The disclosure relates to technology for bulk initialization of memory in a computer system. The computer system comprises a processor core comprising a load store unit and a last level cache in communication with the processor core. The last level cache is configured to receive bulk store operations from the load store unit. Each bulk store operation includes a physical address in the memory to be initialized. The last level cache is configured to send multiple write transactions to the memory for each bulk store operation to perform a bulk initialization of the memory for each bulk store operation. The last level cache is configured to track status of the bulk store operations.

公开(公告)号：US20230004493A1

公开(公告)日：2023-01-05

申请号：US17902263

申请日：2022-09-02

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuejian Xie ,  Qian Wang ,  Xingyu Jiang

IPC: G06F12/0811 ,  G06F12/1009

Abstract: The disclosure relates to technology for bulk initialization of memory in a computer system. The computer system comprises a processor core comprising a load store unit and a last level cache in communication with the processor core. The last level cache is configured to receive bulk store operations from the load store unit. Each bulk store operation includes a physical address in the memory to be initialized. The last level cache is configured to send multiple write transactions to the memory for each bulk store operation to perform a bulk initialization of the memory for each bulk store operation. The last level cache is configured to track status of the bulk store operations.

公开(公告)号：US20220382678A1

公开(公告)日：2022-12-01

申请号：US17886718

申请日：2022-08-12

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yuejian Xie ,  Qian Wang ,  Xingyu Jiang

IPC: G06F12/0802

Abstract: The disclosure relates to technology for up-evicting cache lines. An apparatus comprises a hierarchy of caches comprising a first cache having a first cache controller and a second cache having a second cache controller. The first cache controller is configured to store cache lines evicted from a first processor group to the first cache and to down-evict cache lines from the first cache to the second cache. The second cache controller is configured to store cache lines evicted from a second processor group into the second cache, to up-evict a first cache line from the second cache to the first cache in response to an eviction of a second cache line from the second processor group to the second cache, and to provide the up-evicted first cache line from the first cache to the second processor group in response to a request from the second processor group.