公开(公告)号：US11609787B2

公开(公告)日：2023-03-21

申请号：US16947055

申请日：2020-07-16

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei Liao ,  Yicheng Chen ,  Yu Zhang ,  Hai Jin ,  Jin Zhao ,  Xiang Zhao ,  Beibei Si

IPC: G06F9/48 ,  G06F9/50

Abstract: The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

公开(公告)号：US20210191763A1

公开(公告)日：2021-06-24

申请号：US16947055

申请日：2020-07-16

Applicant: Huazhong University of Science and Technology

Inventor： Xiaofei LIAO ,  Yicheng Chen ,  Yu Zhang ,  Hai Jin ,  Jin Zhao ,  Xiang Zhao ,  Beibei Si

IPC: G06F9/48 ,  G06F30/331 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

Abstract: The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.