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    FPGA-based dynamic graph processing method
    1.
    发明授权
    FPGA-based dynamic graph processing method 有权

    公开(公告)号：US11609787B2

    公开(公告)日：2023-03-21

    申请号：US16947055

    申请日：2020-07-16

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiaofei Liao ,  Yicheng Chen ,  Yu Zhang ,  Hai Jin ,  Jin Zhao ,  Xiang Zhao ,  Beibei Si

    IPC: G06F9/48 ,  G06F9/50

    Abstract: The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

    FPGA-BASED DYNAMIC GRAPH PROCESSING METHOD
    3.
    发明申请
    FPGA-BASED DYNAMIC GRAPH PROCESSING METHOD 有权

    公开(公告)号：US20210191763A1

    公开(公告)日：2021-06-24

    申请号：US16947055

    申请日：2020-07-16

    Applicant: Huazhong University of Science and Technology

    Inventor： Xiaofei LIAO ,  Yicheng Chen ,  Yu Zhang ,  Hai Jin ,  Jin Zhao ,  Xiang Zhao ,  Beibei Si

    IPC: G06F9/48 ,  G06F30/331 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50

    Abstract: The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

    Data storing systems, data storing methods, and electronic devices
    4.
    发明授权
    Data storing systems, data storing methods, and electronic devices 有权

    公开(公告)号：US12197330B2

    公开(公告)日：2025-01-14

    申请号：US18470346

    申请日：2023-09-19

    Applicant: ZHEJIANG LAB ,  Huazhong University of Science and Technology

    Inventor： Zhan Zhang ,  Yu Zhang ,  Jin Zhao ,  Haifei Wu

    IPC: G06F12/0804

    Abstract: The present disclosure provides a data storage system, including data cache module, data processing module, and a persistent memory. The data cache module includes an on-chip mapping data cache and an on-chip counter cache, where the mapping data cache is configured to cache mapping data, and when the free space of the mapping data cache is less than a preset threshold, the least recently used mapping data cache line will be evicted from the cache and written back to the persistent memory. The data processing module encrypts/decrypts persistent memory data by using their counters, and accesses the persistent memory blocks indicated by their corresponding mapping data. The persistent memory comprises the first and second storage regions for the latest checkpoint data and modified working data in the current checkpoint interval respectively.

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