公开(公告)号：US06359608B1

公开(公告)日：2002-03-19

申请号：US08913703

申请日：1997-09-08

申请人： Hughes Lebrun ,  Francois Maurice ,  Eric Sanson ,  Bruno Mourey

发明人： Hughes Lebrun ,  Francois Maurice ,  Eric Sanson ,  Bruno Mourey

IPC分类号： G09G336

CPC分类号： G09G3/3688 ,  G09G3/3648 ,  G09G2310/0205 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/0297 ,  G09G2320/0204

摘要： The present invention relates to a method for addressing a flat screen composed of lines and columns, with pixels located at their intersections, characterized in that, at the start of each sampling of the video signal to be displayed on the screen, a voltage (Vr) higher than the working voltage range (V) is applied to the selected pixel for a time tr, then the working voltage is sampled for a time ts.

摘要翻译： 本发明涉及一种用于寻址由线和列组成的平面屏幕的方法，其中像素位于它们的交点处，其特征在于，在要在屏幕上显示的视频信号的每次采样开始时，电压（Vr ）高于工作电压范围（V）被施加到时间tr的所选像素，则工作电压被采样一段时间ts。

公开(公告)号：US6064713A

公开(公告)日：2000-05-16

申请号：US926536

申请日：1997-09-10

申请人： Hughes Lebrun ,  Fran.cedilla.ois Maurice ,  Eric Sanson

发明人： Hughes Lebrun ,  Fran.cedilla.ois Maurice ,  Eric Sanson

IPC分类号： G09G3/20 ,  G09G3/36 ,  G11C19/00 ,  G11C19/28

CPC分类号： G11C19/28 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0283 ,  G09G2310/0286

摘要： A shift register having several cascaded stages, each stage containing an output at a first node connected to a next stage, a first input connected to an output of a preceding stage, a second input connected to an output of the next stage and a first terminal connected to a first clock signal and a second terminal connected to a second clock signal, the stage containing a first semiconductor device switching the output of the stage between high and low values of the first clock signal, the first semiconductor device being controlled by the potential of a second node, itself connected to the output of the preceding stage across a second semiconductor device controlled by the output of the preceding stage; to a negative potential across a third semiconductor device controlled by the output of the next stage; and to the second terminal connected to the second clock signal across a first capacitance, wherein a second capacitance is mounted between the second node and the output of the next stage.

摘要翻译： 一种具有若干级联级的移位寄存器，每级包含连接到下一级的第一节点处的输出，连接到前一级的输出的第一输入端，连接到下一级输出的第二输入端和第一端子 连接到第一时钟信号和连接到第二时钟信号的第二端子，所述载台包含第一半导体器件，其将所述级的输出切换到所述第一时钟信号的高电平值和低电平值之间，所述第一半导体器件由所述电位 第二节点本身连接到由前一级的输出控制的第二半导体器件的前级的输出; 跨越由下一级的输出控制的第三半导体器件的负电位; 以及跨越第一电容连接到第二时钟信号的第二端子，其中第二电容安装在第二节点和下一级的输出之间。