公开(公告)号：US07880516B2

公开(公告)日：2011-02-01

申请号：US11910062

申请日：2005-03-31

申请人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

发明人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/081 ,  H03L7/1976

摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.

摘要翻译： 一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号和分频信号之间的差。 一种包含锁相环的装置。 锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

公开(公告)号：US20080265958A1

公开(公告)日：2008-10-30

申请号：US11910062

申请日：2005-03-31

申请人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

发明人： Hugues Beaulaton ,  Stephane Colomines ,  Philippe Gorisse

IPC分类号： H03L7/06

CPC分类号： H03L7/0891 ,  H03L7/081 ,  H03L7/1976

摘要： A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.

摘要翻译： 一种用于降低包括至少一个锁相环（PLL）的设备中的噪声的方法，所述方法包括：调整PLL的至少一个可调节分量，以确定时移; 调制分频器，以便在调制噪声周期内产生调制噪声并提供分频信号; 引入调制噪声周期和测量周期之间的时间偏移; 并且在测量周期期间测量参考信号与分频信号之间的差。 一种包含锁相环的装置。 锁相环（PLL）包括：分频器，适于从受控振荡器接收输出信号并提供分频信号; 调制器，适于影响至少一个分频特性并在调制噪声周期期间引入调制噪声;相位检测器，适于在测量周期期间测量参考信号与分频信号之间的差; 以及适于影响调制周期和测量周期之间的可调节时间偏移的可调节延迟单元。

公开(公告)号：US08654006B2

公开(公告)日：2014-02-18

申请号：US13145122

申请日：2009-02-13

申请人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

发明人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

IPC分类号： G01S7/28

CPC分类号： G01S7/35 ,  G01S7/032 ,  G01S13/34 ,  G01S13/931 ,  G01S2013/9325 ,  H03C3/0925 ,  H03L7/1976

摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

摘要翻译： 集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。 频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑 并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。

公开(公告)号：US20110285575A1

公开(公告)日：2011-11-24

申请号：US13145122

申请日：2009-02-13

申请人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

发明人： Christophe Landez ,  Hugues Beaulaton ,  Thierry Cassagnes ,  Stephane Colomines ,  Robert G. Gach ,  Akbar Ghazinour ,  Hao Li ,  Gilles Montoriol ,  Didier Salle ,  Pierre Savary

IPC分类号： G01S13/02

CPC分类号： G01S7/35 ,  G01S7/032 ,  G01S13/34 ,  G01S13/931 ,  G01S2013/9325 ,  H03C3/0925 ,  H03L7/1976

摘要： An integrated circuit comprises frequency generation circuitry for controlling a frequency source for an automotive radar system. The frequency generation circuitry comprises a Phase Locked Loop (PLL) arranged to generate a control signal for controlling the frequency source, a fractional-N divider located within a feedback loop of the PLL, and frequency pattern control logic operably coupled to the fractional-N divider and arranged to control the fractional-N divider, by way of a frequency control signal, such that the PLL generates a Frequency Modulated Continuous Wave (FMCW) control signal.

摘要翻译： 集成电路包括用于控制汽车雷达系统的频率源的频率产生电路。 频率产生电路包括被锁定环路（PLL），该锁相环路被配置为产生用于控制频率源的控制信号，位于PLL的反馈环路内的分数N分频器，以及可操作地耦合到分数N的频率模式控制逻辑 并且被布置成通过频率控制信号来控制分数N分频器，使得PLL产生调频连续波（FMCW）控制信号。