公开(公告)号：US20080001227A1

公开(公告)日：2008-01-03

申请号：US11427409

申请日：2006-06-29

申请人： Huilong Zhu ,  Oleg Gluschenkov ,  Jing Wang

发明人： Huilong Zhu ,  Oleg Gluschenkov ,  Jing Wang

IPC分类号： H01L27/12

CPC分类号： H01L29/78612 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.

摘要翻译： finFet使用两个栅极结构之一来控制传导通道条件，优选地具有比另一个栅极结构更短的栅极长度，以限制在导电沟道上相对的电容。 以与栅极结构相邻的角度执行的用于控制导通通道条件的不对称卤素杂质注入形成了超陡逆行阱，以限制由另一栅极结构控制的导电沟道部分中的短沟道效应。

公开(公告)号：US08227316B2

公开(公告)日：2012-07-24

申请号：US11427409

申请日：2006-06-29

申请人： Huilong Zhu ,  Oleg Gluschenkov ,  Jing Wang

发明人： Huilong Zhu ,  Oleg Gluschenkov ,  Jing Wang

IPC分类号： H01L21/336

CPC分类号： H01L29/78612 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

摘要： A finFet controls conduction channel conditions using one of two gate structures, preferably having a gate length shorter than the other gate structure to limit capacitance, which are opposed across the conduction channel. An asymmetric halo impurity implant performed at an angle adjacent to the gate structure for controlling conduction channel conditions forms a super steep retrograde well to limit short channel effects in the portion of the conduction channel which is controlled by the other gate structure.

摘要翻译： finFet使用两个栅极结构之一来控制传导通道条件，优选地具有比另一个栅极结构更短的栅极长度，以限制在导电沟道上相对的电容。 以与栅极结构相邻的角度执行的用于控制导通通道条件的不对称卤素杂质注入形成了超陡逆行阱，以限制由另一栅极结构控制的导电沟道部分中的短沟道效应。

公开(公告)号：US20130011981A1

公开(公告)日：2013-01-10

申请号：US13614476

申请日：2012-09-13

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

摘要： A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, a metal oxide semiconductor field effect transistor (MOFET) is provided that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions.

摘要翻译： 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，提供了一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 该结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。

公开(公告)号：US08299540B2

公开(公告)日：2012-10-30

申请号：US12754250

申请日：2010-04-05

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L27/06 ,  H01L21/02 ,  H01L29/78 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L21/26586 ,  H01L29/66651 ,  H01L29/7833

摘要： A semiconductor structure which exhibits high device performance and improved short channel effects is provided. In particular, the present invention provides a metal oxide semiconductor field effect transistor (MOFET) that includes a low dopant concentration within an inversion layer of the structure; the inversion layer is an epitaxial semiconductor layer that is formed atop a portion of the semiconductor substrate. The inventive structure also includes a well region of a first conductivity type beneath the inversion layer, wherein the well region has a central portion and two horizontally abutting end portions. The central portion has a higher concentration of a first conductivity type dopant than the two horizontally abutting end portions. Such a well region may be referred to as a non-uniform super-steep retrograde well.

摘要翻译： 提供了具有高器件性能和改善的短沟道效应的半导体结构。 特别地，本发明提供一种金属氧化物半导体场效应晶体管（MOFET），其包括在该结构的反转层内的低掺杂剂浓度; 反型层是形成在半导体衬底的一部分顶上的外延半导体层。 本发明的结构还包括在反转层下面的第一导电类型的阱区，其中阱区具有中心部分和两个水平邻接的端部。 中心部分具有比两个水平邻接端部更高的第一导电类型掺杂剂的浓度。 这样的井区域可以被称为不均匀的超陡逆行井。

公开(公告)号：US20120171842A1

公开(公告)日：2012-07-05

申请号：US13419927

申请日：2012-03-14

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L21/762

CPC分类号： H01L29/7846 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

摘要翻译： 提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。 在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率， 第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

公开(公告)号：US20090309163A1

公开(公告)日：2009-12-17

申请号：US12136970

申请日：2008-06-11

申请人： Jing Wang ,  Huilong Zhu

发明人： Jing Wang ,  Huilong Zhu

IPC分类号： H01L27/092 ,  H01L21/31

CPC分类号： H01L29/7843 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823871

摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack. In an exemplary embodiment, the opening may be extended into an underlying layer such as a source/drain region of the shorter gate stack and a bottom thereof silicided such that a contact formed therein exhibits reduced contact resistance.

摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。 在示例性实施例中，开口可以延伸到下层，例如较短栅极堆叠的源极/漏极区域，并且其底部被硅化，使得其中形成的接触部显示出降低的接触电阻。

公开(公告)号：US20090127626A1

公开(公告)日：2009-05-21

申请号：US11940531

申请日：2007-11-15

申请人： Huilong Zhu ,  Jing Wang

发明人： Huilong Zhu ,  Jing Wang

IPC分类号： H01L21/762 ,  H01L23/58 ,  H01L27/088

CPC分类号： H01L29/7846 ,  H01L21/3081 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

摘要： A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

摘要翻译： 提供了一种浅沟槽隔离结构，其包含第一浅沟槽隔离部分，其包括第一浅沟槽材料和包括第二浅沟槽材料的第二浅沟槽隔离部分。 在至少一个第二有效区域上的至少一个第一有效区域和第二双向应力上的第一双轴应力被分别操纵以通过选择第一和第二有源区域来增强至少一个第一和第二有源区域的中间部分中的载流子迁移率， 第二浅沟槽材料以及调节所述至少一个第一有源区域和所述至少一个第二有源区域的每个部分横向邻接的浅沟槽隔离材料的类型。

公开(公告)号：US20070122961A1

公开(公告)日：2007-05-31

申请号：US11560925

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the pMOSFET device and tensile stress in the channel of the nMOSFET device. One of the pMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极叠层各自被在pMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 pMOSFET或nMOSFET器件中的一个具有比其他相邻器件的高度更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US20070120197A1

公开(公告)日：2007-05-31

申请号：US11561047

申请日：2006-11-17

申请人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce Doris ,  Zhibin Ren

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent PMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的PMOSFET和nMOSFET器件，其中栅极叠层各自被在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。

公开(公告)号：US07183613B1

公开(公告)日：2007-02-27

申请号：US11164224

申请日：2005-11-15

申请人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

发明人： Huilong Zhu ,  Jing Wang ,  Bruce B. Doris ,  Zhibin Ren

IPC分类号： H01L27/01

CPC分类号： H01L21/82385 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843

摘要： A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

摘要翻译： 用于制造的结构和方法包括相邻的pMOSFET和nMOSFET器件，其中栅极堆叠每个都由在PMOSFET器件的沟道中提供压应力的应力层和nMOSFET器件的沟道中的拉伸应力覆盖。 PMOSFET或nMOSFET器件中的一个具有比另一个器件更短的高度，并且两个器件中的较短的器件通过覆盖较短器件的应力层中的不连续或开口来描绘。 在用于形成器件的优选方法中，在具有不同高度的栅极堆叠上形成单个应力层，以在栅极堆叠下的衬底中形成第一类型应力，并且在距离较短栅极堆叠一定距离处的应力层中形成开口 使得在较短的栅极堆叠下形成第二种类型的应力。