公开(公告)号：US07271578B2

公开(公告)日：2007-09-18

申请号：US11131401

申请日：2005-05-18

申请人： Hung Yi Kuo ,  Jenny Chen ,  Jiin Lai

发明人： Hung Yi Kuo ,  Jenny Chen ,  Jiin Lai

IPC分类号： G01R17/06

CPC分类号： G01R19/16552

摘要： A voltage monitoring circuit is capable of being integrated into a chip and monitoring the voltage quality. It mainly uses a first waveshaper to receive a voltage signal of a voltage source to be measured, process it to a logic signal, and output to a first logic level transformer. A first digital signal is transformed by the processing and can be recorded by a register such that a managing system can read content of the register through a bus to further determine whether the voltage source has a situation of voltage surge. Similarly, an inverter can be concatenated between a second waveshaper and a second logic level transformer to monitor whether the voltage source has undercurrent pulse. This way, an object of monitoring voltage quality in the chip with a combination of simple analog circuit can be achieved.

摘要翻译： 电压监测电路能够集成到芯片中并监测电压质量。 它主要使用第一个波形器接收要测量的电压源的电压信号，将其处理为逻辑信号，并输出到第一逻辑电平变压器。 第一数字信号通过处理变换，并且可以由寄存器记录，使得管理系统可以通过总线读取寄存器的内容，以进一步确定电压源是否具有电压浪涌的情况。 类似地，逆变器可以连接在第二波形与第二逻辑电平变换器之间，以监测电压源是否具有欠电流脉冲。 这样，可以实现利用简单模拟电路的组合来监视芯片中的电压质量的目的。

公开(公告)号：US07532039B2

公开(公告)日：2009-05-12

申请号：US11648593

申请日：2007-01-03

申请人： Hung Yi Kuo ,  Janqlih Hsieh ,  Jenny Chen ,  Hueilin Chou

发明人： Hung Yi Kuo ,  Janqlih Hsieh ,  Jenny Chen ,  Hueilin Chou

IPC分类号： H03D13/00

CPC分类号： G06F1/12

摘要： A clock signal detector is provided. The device comprises a plurality of signal delayers and a plurality of flip-flops for comparing the offset range of the clock signal between two different groups, and transmitting the resulted signal to a phase compensator, which is used to send a regulating clock signal to a clock generator. Therefore, the offset ranges of the clock signals from two different groups will be within the range of the system requirement, such that it can optimize the system operation.

摘要翻译： 提供时钟信号检测器。 该装置包括多个信号延迟器和多个触发器，用于比较两个不同组之间的时钟信号的偏移范围，并将得到的信号发送到相位补偿器，该相位补偿器用于将调节时钟信号发送到 时钟发生器。 因此，来自两个不同组的时钟信号的偏移范围将在系统要求的范围内，从而可以优化系统的运行。

公开(公告)号：US07508237B2

公开(公告)日：2009-03-24

申请号：US11094282

申请日：2005-03-31

申请人： Hung Yi Kuo ,  Jenny Chen ,  Huei-Lin Chou

发明人： Hung Yi Kuo ,  Jenny Chen ,  Huei-Lin Chou

IPC分类号： H03K19/00

CPC分类号： G06F1/3203 ,  G06F1/329 ,  Y02D10/24

摘要： A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.

摘要翻译： 逻辑运算的控制方法用于控制处于功率峰值状态的芯片内部的多个逻辑。 控制方法包括以下步骤：向芯片提供控制信号，在第一定时基于控制信号控制逻辑中的至少一个，并根据控制信号控制至少另一个逻辑 第二时间。 控制信号旨在同步地基本上控制逻辑的动作。 此外，提供利用逻辑操作的控制方法的主板和电子部件。