公开(公告)号：US06330199B2

公开(公告)日：2001-12-11

申请号：US09741162

申请日：2000-12-21

申请人： Hyun Taek Jung ,  Gyu Hong Kim

发明人： Hyun Taek Jung ,  Gyu Hong Kim

IPC分类号： G11C700

CPC分类号： G11C29/808 ,  G11C29/846

摘要： In a semiconductor memory device having redundancy capability, a control signal generating circuit is included respectively for each of a predetermined number of redundant column select signal lines, to generate a predetermined number of block control signals by dividing a plurality of memory cell array blocks into a predetermined number of groups. A predetermined number of defective enable signal generating circuits are included for each of the redundant column select signal lines, to generate a predetermined number of redundant enable signals when defective addresses are input. The redundant column select signal lines are established for defective addresses based on the block control signals. A selection circuit is included respectively for each of the redundant column select signal lines to generate a select signal for selecting a redundant column select signal line corresponding to each of a predetermined number of redundant enable signals, in response to the block control signals. The efficiency of redundancy is thus improved by performing a redundancy operation by dividing a plurality of memory cell arrays into a predetermined number of groups for each of redundant column select signals.

公开(公告)号：US20120300560A1

公开(公告)日：2012-11-29

申请号：US13477448

申请日：2012-05-22

申请人： Suk-Soo Pyo ,  Hyun Taek Jung

发明人： Suk-Soo Pyo ,  Hyun Taek Jung

IPC分类号： G11C7/06

CPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/417 ,  G11C11/419

摘要： A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括多个字线，多个位线，包括互补的位线对以及存储数据的多个存储单元; 感测放大器，耦合到所述存储单元阵列并且被配置为感测所述互补的位线对之间的电压差，并且放大所述电压差; 以及至少一个电压驱动器，被配置为向存储单元阵列提供预定电压或第一电源电压以增加半导体存储器件的感测裕度。 半导体存储器件使用在存储单元阵列中隔离的电压来增加互补的位线对之间的各自的电位差。

公开(公告)号：US08644094B2

公开(公告)日：2014-02-04

申请号：US13477448

申请日：2012-05-22

申请人： Suk-Soo Pyo ,  Hyun Taek Jung

发明人： Suk-Soo Pyo ,  Hyun Taek Jung

IPC分类号： G11C7/06

CPC分类号： G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/417 ,  G11C11/419

摘要： A semiconductor memory device includes a memory cell array including a plurality of word lines, a plurality of bit lines including complementary pairs of bit lines, and a plurality of memory cells storing data; a sense amplifier coupled to the memory cell array and configured to sense voltage differences between the complementary pairs of bit lines and amplify the voltage differences; and at least one voltage driver configured to provide either a predetermined voltage or a first power supply voltage to the memory cell array to increase a sensing margin of the semiconductor memory device. The semiconductor memory device increases respective potential differences between complementary pairs of bit lines using a voltage isolated in the memory cell array.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括多个字线，多个位线，包括互补的位线对以及存储数据的多个存储单元; 感测放大器，耦合到所述存储单元阵列并且被配置为感测所述互补的位线对之间的电压差，并且放大所述电压差; 以及至少一个电压驱动器，被配置为向存储单元阵列提供预定电压或第一电源电压以增加半导体存储器件的感测裕度。 半导体存储器件使用在存储单元阵列中隔离的电压来增加互补的位线对之间的各自的电位差。