公开(公告)号：US07843736B2

公开(公告)日：2010-11-30

申请号：US12396937

申请日：2009-03-03

申请人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

发明人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/28

摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

摘要翻译： 公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。 如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。 如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

公开(公告)号：US20090231922A1

公开(公告)日：2009-09-17

申请号：US12396937

申请日：2009-03-03

申请人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

发明人： Hyung-Seok Kang ,  Eui-Gyu Han ,  Hoo-Sung Kim

IPC分类号： G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/28

摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.

摘要翻译： 公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。 如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。 如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

公开(公告)号：US08089804B2

公开(公告)日：2012-01-03

申请号：US11810554

申请日：2007-06-06

申请人： Hoo-Sung Kim ,  Eui-Gyu Han

发明人： Hoo-Sung Kim ,  Eui-Gyu Han

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3422 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

摘要翻译： 非易失性半导体存储器被配置为监视读取干扰的开始（例如，由于软编程），并执行用于保护其中的数据的操作。 非易失性半导体存储器具有包括正常存储单元和标志存储单元的存储单元阵列。 标记存储单元被配置为比其比正常存储器单元更容易受到其对数据保持的电应力。 存储器监视存储在标志存储单元中的数据，以监视正常存储器单元的数据保持特性。

公开(公告)号：US20080106935A1

公开(公告)日：2008-05-08

申请号：US11810554

申请日：2007-06-06

申请人： Hoo-Sung Kim ,  Eui-Gyu Han

发明人： Hoo-Sung Kim ,  Eui-Gyu Han

IPC分类号： G11C16/34

CPC分类号： G11C16/3418 ,  G11C16/3422 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529

摘要： A non-volatile semiconductor memory is configured to monitor for onset of a read disturbance (e.g., due to soft programming) and to carry out operations to protect data therein. A non-volatile semiconductor memory has a memory cell array that includes normal memory cells and a flag memory cell. The flag memory cell is configured to be more susceptible to electrical stress on its retention of data than the normal memory cells. The memory monitors data stored in the flag memory cell to monitor a data retention characteristic of the normal memory cells.

摘要翻译： 非易失性半导体存储器被配置为监视读取干扰的开始（例如，由于软编程），并执行用于保护其中的数据的操作。 非易失性半导体存储器具有包括正常存储单元和标志存储单元的存储单元阵列。 标记存储单元被配置为比其比正常存储器单元更容易受到其对数据保持的电应力。 存储器监视存储在标志存储单元中的数据，以监视正常存储器单元的数据保持特性。

公开(公告)号：US07272050B2

公开(公告)日：2007-09-18

申请号：US11060915

申请日：2005-02-17

申请人： Eui-Gyu Han ,  Kil-Yeon Kim ,  Gyeong-Soo Han

发明人： Eui-Gyu Han ,  Kil-Yeon Kim ,  Gyeong-Soo Han

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

摘要翻译： 一种非易失性存储器件的擦除方法，包括排列成行和列的矩阵的存储单元。 存储单元同时被擦除。 对擦除的存储单元执行擦除验证操作。 在行的不同偏置条件下重复擦除方法。 擦除验证操作在字线的不同偏置条件下连续执行两次或更多次，以减少由在过程中产生的弱电池引起的电池电流。 因此，增强擦除验证操作的可靠性以增加产量。

公开(公告)号：US20060034128A1

公开(公告)日：2006-02-16

申请号：US11060915

申请日：2005-02-17

申请人： Eui-Gyu Han ,  Kil-Yeon Kim ,  Gyeong-Soo Han

发明人： Eui-Gyu Han ,  Kil-Yeon Kim ,  Gyeong-Soo Han

IPC分类号： G11C16/04 ,  G11C7/00 ,  G11C11/34

CPC分类号： G11C16/3445 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/344

摘要： An erase method of a non-volatile memory device including memory cells arranged in a matrix of rows and columns. The memory cells are erased at the same time. An erase-verify operation is performed for the erased memory cells. The erase method is repeated under different bias conditions of the rows. An erase-verify operation is successively performed twice or more under different bias conditions of wordlines to decrease cell current caused by a weak cell which may be produced in a process. Thus, a reliability of an erase-verify operation is enhance to increase a yield.

摘要翻译： 一种非易失性存储器件的擦除方法，包括排列成行和列的矩阵的存储单元。 存储单元同时被擦除。 对擦除的存储单元执行擦除验证操作。 在行的不同偏置条件下重复擦除方法。 擦除验证操作在字线的不同偏置条件下连续执行两次或更多次，以减少由在过程中产生的弱电池引起的电池电流。 因此，增强擦除验证操作的可靠性以增加产量。

公开(公告)号：US06201432B1

公开(公告)日：2001-03-13

申请号：US09315695

申请日：1999-05-20

申请人： Ki-Won Lim ,  Eui-Gyu Han ,  Jeong-Un Choi

发明人： Ki-Won Lim ,  Eui-Gyu Han ,  Jeong-Un Choi

IPC分类号： H01H3776

CPC分类号： G11C17/18

摘要： Integrated circuit devices include a comparator circuit and a fuse programmable input circuit. The fuse programmable input circuit generates first and second differential input signals at voltage levels that can be controlled through a pair of fuses. The comparator circuit generates an output signal based on the relative voltage levels exhibited by the first and second differential input signals. In particular, the output signal is driven to a first logic state when the voltage difference between the first and second differential input signals is positive and the output signal is driven to a second logic state, which is opposite the first logic state, when the voltage difference is negative. Because the comparator is responsive to the relative difference between the voltage levels of the first and second differential input signals and not the absolute magnitudes of the voltage levels, fuse remnants that may exist after the fuse programmable input circuit has been programmed (i.e., one or more fuses have been cut) typically do not affect the output signal.

摘要翻译： 集成电路器件包括比较器电路和熔丝可编程输入电路。 保险丝可编程输入电路在可通过一对保险丝控制的电压电平下产生第一和第二差分输入信号。 比较器电路基于由第一和第二差分输入信号表现的相对电压电平产生输出信号。 具体地，当第一和第二差分输入信号之间的电压差为正时，输出信号被驱动到第一逻辑状态，并且当电压与第一逻辑状态相反时，输出信号被驱动到第二逻辑状态 差异为负数。 因为比较器响应于第一和第二差分输入信号的电压电平之间的相对差异而不是电压电平的绝对值，所以在熔丝可编程输入电路已被编程之后可能存在的熔丝残余物（即，一个或多个 更多的保险丝被切断）通常不影响输出信号。