公开(公告)号：US3927311A

公开(公告)日：1975-12-16

申请号：US49889874

申请日：1974-08-20

Applicant: IBM

Inventor： CHEN TIEN C ,  HO IRVING T

IPC: G06F7/491 ,  G06F7/52

CPC classification number: G06F7/4915 ,  G06F7/4917

Abstract: An arithmetic system employing logic arrays for performing decimal halving and doubling is disclosed. Equal weighted wire matrix read only memory techniques are employed in the logic arrays to conserve required computational hardware and to facilitate large-scale circuit integration (LSI). The logic arrays are addressed by an input register containing a binary coded decimal (BCD) number, and the halved or doubled output in BCD form is read out in parallel into an output register.

Abstract translation: 公开了一种采用逻辑阵列执行十进制加倍和倍增的算术系统。 在逻辑阵列中采用等加权线矩阵只读存储器技术来节省所需的计算硬件并促进大规模电路集成（LSI）。 逻辑阵列由包含二进制编码十进制（BCD）编号的输入寄存器寻址，BCD形式的一半或双倍输出并行读出到一个输出寄存器中。