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公开(公告)号：US3662351A
公开(公告)日：1972-05-09
申请号：US3662351D
申请日：1970-03-30
Applicant: IBM
Inventor： HO IRVING T , MALEY GERALD A , WAXMAN RONALD
IPC: G11C7/20 , G11C11/411 , G11C16/04 , G11C17/08 , H01L27/10 , H01L27/105 , H03K3/356 , G11C11/00 , G11C17/00
CPC classification number: H03K3/356008 , G11C7/20 , G11C11/4116 , G11C16/0466 , G11C17/08 , H01L27/10 , H01L27/105
Abstract: A monolithic latent image memory is one having a plurality of bistable memory cells. Selected bistable memory cells include AC impedance means which are responsive at the transition from nonsustaining voltage level to an operating level so as to set the selected memory cells to a first predetermined state and thus provide a monolithic memory which is capable of functioning in a read-only and a read-write mode. The read-only state is selectively alterable by employing an AC impedance means which is multi-valued.
Abstract translation: 单片潜像存储器是具有多个双稳态存储单元的潜像存储器。 所选择的双稳态存储器单元包括AC阻抗装置，其在从非维持电压电平转换到工作电平时响应，以便将所选择的存储器单元设置为第一预定状态，从而提供能够在 只读和读写模式。 通过使用多值的AC阻抗装置可选地改变只读状态。
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公开(公告)号：US3569945A
公开(公告)日：1971-03-09
申请号：US3569945D
申请日：1969-01-06
Applicant: IBM
Inventor： HO IRVING T
CPC classification number: G11C11/36
Abstract: A PNPN semiconductor diode is connected in series with an additional PN diode to form a bit memory. A bit is stored on the PNPN device by applying a positive voltage sufficiently large to break down the center junction of the PNPN device and increase the minority carriers in the regions adjacent to the center junction. Repetitive small positive voltage pulses maintain the minority carrier condition as a bit memory. A large negative voltage erases the memory cell.
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公开(公告)号：US3927311A
公开(公告)日：1975-12-16
申请号：US49889874
申请日：1974-08-20
Applicant: IBM
Inventor： CHEN TIEN C , HO IRVING T
CPC classification number: G06F7/4915 , G06F7/4917
Abstract: An arithmetic system employing logic arrays for performing decimal halving and doubling is disclosed. Equal weighted wire matrix read only memory techniques are employed in the logic arrays to conserve required computational hardware and to facilitate large-scale circuit integration (LSI). The logic arrays are addressed by an input register containing a binary coded decimal (BCD) number, and the halved or doubled output in BCD form is read out in parallel into an output register.
Abstract translation: 公开了一种采用逻辑阵列执行十进制加倍和倍增的算术系统。 在逻辑阵列中采用等加权线矩阵只读存储器技术来节省所需的计算硬件并促进大规模电路集成（LSI）。 逻辑阵列由包含二进制编码十进制（BCD）编号的输入寄存器寻址，BCD形式的一半或双倍输出并行读出到一个输出寄存器中。
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公开(公告)号：US3676863A
公开(公告)日：1972-07-11
申请号：US3676863D
申请日：1970-03-11
Applicant: IBM
Inventor： HO IRVING T
CPC classification number: G11C19/182
Abstract: A monolithic memory including a plurality of interconnected cells. Each cell includes a diode in series with bipolar device or transistor which is dynamically or pulse powered. Parasitic capacitors are used as storage elements.
Abstract translation: 包括多个互连电池的单片存储器。 每个单元包括与双极器件或晶体管串联的二极管，其被动态或脉冲供电。 寄生电容用作存储元件。
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Patent Agency Ranking
公开(公告)号：US3665210A
公开(公告)日：1972-05-23
申请号：US3665210D
申请日：1970-06-30
Applicant: IBM
Inventor： HO IRVING T , HOWELL PETER E , JEN TEH-SEN
CPC classification number: G11C19/182 , G11C19/28
Abstract: A storage cell suitable for implementation as a monolithic shift register in which a pair of monolithic parasitic capacitors are selectively charged solely in response to periodic non-dc signals to set the digital state of the storage cell. Semiconductor switching means connected between the first and second capacitors is responsive to periodic signals to regenerate the cell for operation in a static mode. Alternatively, a dc circuit prevents loss of cell information during a static mode. The semiconductor switching means is virtually eliminated from the circuit by proper biasing so as to also render the cell operable for use in a dynamic shift register mode.
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公开(公告)号：US3644850A
公开(公告)日：1972-02-22
申请号：US3644850D
申请日：1969-06-11
Applicant: IBM
Inventor： HO IRVING T
IPC: H03H7/06 , H01L21/822 , H01L27/04 , H01P1/201 , H01P3/08
CPC classification number: H01P1/201
Abstract: A semiconductor band pass filter is disclosed. The filter is an integrated circuit device having a semiconductor layer with a ground plane on one face and an insulating layer and an overlying conductive line on the other face. The semiconductor layer includes near the insulating layer a highly doped region which may have substantially the same pattern as the conductive line. The passed band can be selected by varying the doping level of the doped region.
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公开(公告)号：US3697962A
公开(公告)日：1972-10-10
申请号：US3697962D
申请日：1970-11-27
Applicant: IBM
Inventor： BEAUSOLEIL WILLIAM F , HO IRVING T , JEN TEH-SEN , PRICER W DAVID
IPC: G11C11/403 , G11C11/406 , G11C11/4067 , G11C11/4094 , H01L23/535 , H01L27/07 , H01L27/102 , G11C11/40
CPC classification number: H01L27/1023 , G11C11/403 , G11C11/406 , G11C11/4067 , G11C11/4094 , H01L23/535 , H01L27/075 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
Abstract: This specification discloses a stored charged storage cell for implementation in monolithic memories. The storage cells are fabricated in an array form and are connected to accessing means for reading and writing information into and out of the array. An integrated circuit diffused common sensing line is connected to either selected rows or columns for reading and writing. These sensing lines are connected to a switchable current source. The cell itself clamps the output voltage swing and thus reduces power dissipation. The storage cells each comprise a pair of semiconductor elements for storing digital information on an associated parasitic capacitor. The pair of semiconductor devices are interconnected and operated in an AC mode so as to eliminate direct current paths and thus further prevent unnecessary power dissipation.
Abstract translation: 本说明书公开了一种用于在单片存储器中实现的存储的充电存储单元。 存储单元以阵列形式制造并连接到用于将信息读入和写入阵列的访问装置。 集成电路漫射的公共感测线路连接到所选择的行或列用于读取和写入。 这些感测线路连接到可切换的电流源。 电池本身夹紧输出电压摆幅，从而降低功耗。 存储单元各自包括一对半导体元件，用于在关联的寄生电容器上存储数字信息。 该对半导体器件以AC模式互连和操作，以消除直流电流路径，从而进一步防止不必要的功率耗散。
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公开(公告)号：US3500255A
公开(公告)日：1970-03-10
申请号：US3500255D
申请日：1968-04-08
Applicant: IBM
Inventor： HO IRVING T , MULLICK SATISH K
CPC classification number: H01P5/185
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