公开(公告)号：US3919701A

公开(公告)日：1975-11-11

申请号：US35166573

申请日：1973-04-16

Applicant: IBM

Inventor： CHANG HSU ,  CHEN TIEN CHI ,  TUNG CHIN

IPC: G06F7/48 ,  G11C11/14 ,  H03K19/168 ,  G11C19/00

CPC classification number: H03K19/168

Abstract: A symmetric switching device which can be personalized to do any mathematical operation relying upon the mounting of the number of bubble domains present. This can be used as a universal logic element to provide any logical function. The device will handle multiple inputs and is rewritable to provide the desired function. The device broadly comprises a counter for counting the number of 1 bits in the input data stream, a means for producing a control data stream for personalizing the switch, and a comparison means for comparing the counter output and the control stream. A particularly suitable embodiment comprises a bubble domain sifter for shifting the position of the bubbles in the input data stream, a leading bubble detector for detecting the leading (first) bubble in the input data stream, means for creating a personalized control bubble stream for designating the function to be performed, and means for comparing the personalized control bubble stream with the output of the leading bubble detector to provide a circuit output representing the output value of the function desired. Means are provided for serial or parallel data inputs to the symmetric switching circuit. Any known type of domain propagation structure can be used to implement this device.

Abstract translation: 一种对称开关装置，其可以被个性化以进行任何数学运算，这依赖于存在的气泡域的数量的安装。 这可以用作通用逻辑元件来提供任何逻辑功能。 该设备将处理多个输入，并且是可重写的，以提供所需的功能。 该设备广泛地包括用于对输入数据流中的1位数进行计数的计数器，用于产生用于个性化该开关的控制数据流的装置，以及用于比较计数器输出和控制流的比较装置。 特别合适的实施例包括用于移动输入数据流中的气泡位置的气泡域筛选器，用于检测输入数据流中的引导（第一）气泡的前导气泡检测器，用于创建个性化控制气泡流的装置，用于指定 要执行的功能，以及用于将个性化控制气泡流与前导气泡检测器的输出进行比较以提供表示所需功能的输出值的电路输出的装置。 提供用于对称开关电路的串行或并行数据输入的装置。 可以使用任何已知类型的域传播结构来实现该设备。

公开(公告)号：US3631230A

公开(公告)日：1971-12-28

申请号：US3631230D

申请日：1970-09-24

Applicant: IBM

Inventor： CHEN TIEN CHI

IPC: G06F7/544 ,  G06F7/48 ,  G06F7/52

CPC classification number: G06F7/544

Abstract: Apparatus and a method is described for efficiently achieving arithmetic evaluations for functions such as exponential, logarithm, quotient, and square root with a minimum use of multiplications or divisions. Basically, use is made of the fact that x(1 + OR - 2 m) can be evaluated by a shift followed by an add. A pair of numbers (xk, yk) can represent a function x: f(x) g(xk, yk), such that g (l, yn) yn for logarithm, quotient and square root. Then, multiplication by shifting is applied to xk with suitable adjustments on yk, until xk is close to unity, at which time yk represents the desired answer. The exponential is computed by essentially reversing the logarithm procedure. A termination algorithm further improves accuracy. The apparatus involves two registers for xk and yk, a local memory, an adder and a shift register.