公开(公告)号：US3317899A

公开(公告)日：1967-05-02

申请号：US31823263

申请日：1963-10-23

Applicant: IBM

Inventor： CHIEN ROBERT T ,  FREIMAN CHARLES V

IPC: G06F17/30

CPC classification number: G06F17/30949

公开(公告)号：US3353155A

公开(公告)日：1967-11-14

申请号：US33417863

申请日：1963-12-30

Applicant: IBM

Inventor： CHIEN ROBERT T ,  STEIN JACK J

IPC: H03M13/19

CPC classification number: H03M13/19

公开(公告)号：US3582878A

公开(公告)日：1971-06-01

申请号：US3582878D

申请日：1969-01-08

Applicant: IBM ,  ROBERT T CHIEN

Inventor： BOSSEN DOUGLAS C ,  CHIEN ROBERT T ,  HSIAO MU-YUE ,  SELLERS FREDERICK F JR

IPC: H03M13/19 ,  H04L1/00 ,  H04L1/10 ,  G08C25/00

CPC classification number: H04L1/0057 ,  H03M13/19 ,  H04L1/0041

Abstract: The error correcting system is capable of correcting multiple random errors in data messages of k m2 data bits where m is an integer. The message is encoded by adding 2m check bits for each additional error correcting capability. The encoded message after data transfer and storage is decoded by parity checking and threshold logic decision circuits. The parity checking circuits are constructed in modular form. Each additional module adds a further error correcting capability. The outputs from each module form inputs to the threshold logic decision circuit where the error correction is made. Detection of an additional error can be simply achieved by an overall parity circuit.

公开(公告)号：US3418629A

公开(公告)日：1968-12-24

申请号：US35889364

申请日：1964-04-10

Applicant: IBM

Inventor： CHIEN ROBERT T

IPC: G06F7/72 ,  H03M13/15

CPC classification number: G06F7/724 ,  H03M13/151

公开(公告)号：US3278729A

公开(公告)日：1966-10-11

申请号：US24470262

申请日：1962-12-14

Applicant: IBM

Inventor： CHIEN ROBERT T

IPC: H03M13/15

CPC classification number: H03M13/151

公开(公告)号：US3145306A

公开(公告)日：1964-08-18

申请号：US4871260

申请日：1960-08-10

Applicant: IBM

Inventor： CHIEN ROBERT T

CPC classification number: H03K17/81