公开(公告)号：US3577036A

公开(公告)日：1971-05-04

申请号：US3577036D

申请日：1969-05-05

Applicant: IBM

Inventor： CURTIS JOHN J ,  RUOFF CARL E

IPC: H01L21/74 ,  H01L21/768 ,  H01L23/535 ,  H01L27/00 ,  H01L29/41 ,  H01L19/00

CPC classification number: H01L23/535 ,  H01L21/743 ,  H01L21/768 ,  H01L27/00 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Minimum connection area and maximum reliability over long periods of use are achieved with the improved technique for interconnecting two-level metalization patterns overlying monolithic integrated circuit chips. A pair of metal conductors from each of two levels are joined to each other and are further separately joined to contiguous portions of an isolated low resistivity region in the chip. It has been found that each connection between metalization patterns of two different levels can be effected in an area as small as approximately two-tenths mil by five-tenths mil.