Abstract:
AN INTEGRATED BIPOLAR TRANSISTOR CIRCUIT OF THE RESISTORTRANSISTOR LOGIC TYPE IS FORMED ON A SINGLE SEMICONDUCTOR CHIP, AND INTERCONNECTIONS FROM TRANSISTOR OUTPUT ELECTRODES AND I/O (INPUT/OUTPUT) CHIP TERMINALS TO TRANSISTOR INPUT ELECTRODES ARE PROVIDED BY MEANS OF HIGH AND LOW RESISTIVITY REGIONS WITHIN THE CHIP AND BY A SELECTED METALLIZATION PATTERN FORMED IN A SINGLE PLANE ABOVE AND ISOLATED FROM THE CHIP.
Abstract:
Minimum connection area and maximum reliability over long periods of use are achieved with the improved technique for interconnecting two-level metalization patterns overlying monolithic integrated circuit chips. A pair of metal conductors from each of two levels are joined to each other and are further separately joined to contiguous portions of an isolated low resistivity region in the chip. It has been found that each connection between metalization patterns of two different levels can be effected in an area as small as approximately two-tenths mil by five-tenths mil.