公开(公告)号：US3631229A

公开(公告)日：1971-12-28

申请号：US3631229D

申请日：1970-09-30

Applicant: IBM

Inventor： BENS FREDERICK N ,  DIMITRI KAMAL E ,  MOORE MICHAEL J ,  TOMKO JOHN E ,  WAJDA WALTER W

IPC: G01R31/319 ,  G11C29/56 ,  G01R15/12

CPC classification number: G01R31/31917 ,  G11C29/56

Abstract: A method and apparatus are disclosed for testing on a simulated real time basis a chip or monolithic memory array. The tester is interfaced to a computer with which it communicates in a cycle steal mode of operation. The test pattern which tests the basic failure modes that can occur in the array is loaded into an area of the computer core storage whose address is given to the tester by an instruction. Another core address is given to the tester which is the area where results of the test are stored. A failure diagnosis program makes a decision as to which failure mode occurred, and the results of the diagnosis are printed out with digital coding to indicate the type of failure. Since the entire test is done in continuous cycle steal mode, the time involved is only a few milliseconds, depending on the length of the pattern.