中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

6 records (took 0.021 seconds)

    Data processing system
    4.
    发明授权
    Data processing system 失效

    公开(公告)号：US3077580A

    公开(公告)日：1963-02-12

    申请号：US83845759

    申请日：1959-09-08

    Applicant: IBM

    Inventor： UNDERWOOD FRANCIS O

    IPC: G06F9/30 ,  G06F12/04

    CPC classification number: G06F9/382 ,  G06F9/30149 ,  G06F9/30152 ,  G06F12/04

    Abstract: 954,802. Digital electric calculating. INTERNATIONAL BUSINESS MACHINES CORPORATION. Aug. 24,1960 [Sept. 8, 1959], No. 29205/60. Heading G4A. In a data processing machine the address of a character in store is held. in a register and on the character being read out in modified to give the address of the next character. The store is a magnetic core matrix of which the basic cycle is read-out character to register, process character, return character to original location. It is during the read out that address modification invariably takes place. The machine operates in variable length words of which the end is indicated by a word mark, held in a special core plane, in the first character of the next word. An instruction contains a single letter operation character always accompanied by a word mark, which is usually followed by a three digit A address which may be followed by a three digit B address. The instruction may be completed by an operation modify character which is not described in detail. The address of the word is the storage location of the first character to be read out. The machine operates to three cycles as follows: I-cycle. An instruction word is read out. The address is held in I memory address register 29 and is interpreted in register 21 to set coordinate switches 17,19. As the character is read out to B register 23 the I-address is incremented by one in modifier 35. From the B register the character is read into operation register 27 and also back into storage 11. The incremented address in register 29 then causes the first digit of the A address to be read in to the B register, the contents of the B register are transferred to A memory address register 33 (AMAR) and back to store 11. The I-cycle continues under control of a ring counter (Fig. 4 not shown) until a word mark is read in to the B register 23. When the mark is detected the address in IMAR 29 will have been incremented but the unincremented address in register 21 is passed through modifier 35 unchanged to replace the address in IMAR 29. At the same time the contents of B register 23 are returned to store. A cycle: the character at the address specified by AMAR 33 is read out to the B register 23 while the A address is modified. The contents of the B register are transferred to the A register 25. The contents of the A register i.e. the original character are read back into store. B cycle: the character at the address specified by BMAR 31 is read out to B register 23 while the B address is modified. The contents of the A and B registers are sampled and as a result the character in either register or a new character generated by inhibit circuits 45 is read in to store at the location from which read out took place. When a character is taken from the A register A and B cycles immediately follow. A B cycle may be followed by any form of cycle: an I-cycle is started by detection of a word mark during a B cycle. The control circuits consisting mainly of interacting latches generating signals initiating the various cycles are described (Figs. 3 to 5 and 7, not shown). The Specification refers to Specification 954,801 which describes an edit operation using the present machine.

Patent Agency Ranking