公开(公告)号：US20240354259A1

公开(公告)日：2024-10-24

申请号：US18732865

申请日：2024-06-04

申请人： Texas Instruments Incorporated

发明人： Asheesh Bhardwaj ,  Mujibur Rahman ,  Timothy David Anderson

IPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

摘要： A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

公开(公告)号：US12106206B2

公开(公告)日：2024-10-01

申请号：US17148432

申请日：2021-01-13

申请人： Apple Inc.

发明人： Christopher L. Mills ,  Sung Hee Park

IPC分类号： G06F7/24 ,  G06F7/50 ,  G06F7/523 ,  G06F7/544 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06F7/24 ,  G06F7/50 ,  G06F7/523 ,  G06F7/5443

摘要： Embodiments relate to a neural engine circuit of a neural network processor circuit that performs a convolution operation on input data in a first mode and a parallel sorting operation on input data in a second mode. The neural engine circuit includes a plurality of operation circuits and an accumulator circuit coupled to the plurality of operation circuits. The plurality of operation circuits receives input data. In the first mode, the plurality of operation circuits performs multiply-add operations of a convolution on the input data using a kernel. In the second mode, the plurality of operation circuits performs a portion of a parallel sorting operation on the input data. In the first mode, the accumulator circuit receives and stores first results of the multiply-add operations. In the second mode, the accumulator circuit receives and stores second results of the parallel sorting operation.

公开(公告)号：US20240311313A1

公开(公告)日：2024-09-19

申请号：US18660120

申请日：2024-05-09

申请人： Texas Instruments Incorporated

发明人： Timothy David Anderson ,  Mujibur Rahman

IPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F15/78 ,  G06F17/16 ,  H03H17/06

CPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

摘要： Various configurations of processors are provided. In a configuration, the processor comprises first and second multiplication units. The first multiplication unit includes first multiply circuitry including a first set of outputs; and first multiplexing logic coupled to the first set of outputs and configured to generate a first partial sum and a first partial carry. The second multiplication unit includes second multiply circuitry including a second set of outputs; and second multiplexing logic coupled to the second set of outputs and configured to generate a second partial sum and a first partial carry.

公开(公告)号：US20240281439A1

公开(公告)日：2024-08-22

申请号：US18648342

申请日：2024-04-27

申请人： Ocient Inc.

发明人： Jason Arnold ,  George Kondiles

IPC分类号： G06F16/2453 ,  G06F3/06 ,  G06F7/24 ,  G06F9/4401 ,  G06F9/50 ,  G06F11/10 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/17 ,  G06F16/22 ,  G06F16/23 ,  G06F16/242 ,  G06F16/2455 ,  G06F16/2457 ,  G06F16/2458 ,  G06F16/27 ,  G06F16/901 ,  H03M7/30 ,  H04L67/10

CPC分类号： G06F16/24542 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/068 ,  G06F7/24 ,  G06F9/4406 ,  G06F9/5016 ,  G06F9/5027 ,  G06F9/5061 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/1076 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/1727 ,  G06F16/22 ,  G06F16/2246 ,  G06F16/2282 ,  G06F16/2365 ,  G06F16/244 ,  G06F16/2445 ,  G06F16/2453 ,  G06F16/24553 ,  G06F16/24573 ,  G06F16/2458 ,  G06F16/278 ,  G06F16/901 ,  G06F16/9017 ,  H03M7/30 ,  H04L67/10 ,  G06F3/067 ,  G06F16/24547 ,  G06F2211/1011 ,  G06F2212/608

摘要： A method includes receiving, by a first computing entity of a database system, a query request that is formatted in accordance with a generic query format. The method further includes generating, by the first computing entity, an initial query plan based on the query request and a query instruction set. The method further includes determining, by the first computing entity, storage parameters. The method further includes determining, by the first computing entity, processing resources for processing the query request based on the storage parameters. The method further includes generating, by the first computing entity, an optimized query plan from the initial query plan based on the storage parameters, the processing resources, and optimization tools. The method further includes sending, by the first computing entity, the optimized query plan to a second computing entity for distribution and execution of the optimized query plan.

公开(公告)号：US20240265487A1

公开(公告)日：2024-08-08

申请号：US18433823

申请日：2024-02-06

申请人： Intel Corporation

发明人： Saikat MANDAL ,  Prasoonkumar SURTI ,  Sven WOOP

IPC分类号： G06T1/20 ,  G06F7/02 ,  G06F7/24 ,  G06F7/505 ,  G06F9/38 ,  G06T15/00 ,  G06T15/08 ,  G06T17/10

CPC分类号： G06T1/20 ,  G06F7/02 ,  G06F7/24 ,  G06F7/505 ,  G06F9/3885 ,  G06T15/005 ,  G06T15/08 ,  G06T17/10

摘要： Apparatus and method for stable and short latency sorting. For example, one embodiment of a processor comprises: an input circuit to receive a set of N input values to be sorted into a sorted order; comparison circuitry to compare each input value with all other input values in parallel to generate at least N*(N−1)/2 comparison result values; matrix generation circuitry and/or logic to generate a result matrix having a row associated with each input value, a plurality of bits in each row comprising comparison result values indicating results of comparisons with other input values, wherein a first region of the result matrix is to store a first set of bits comprising the N*(N−1)/2 comparison result values and a second region of the result matrix, opposite the first region, is to store a second set of bits comprising an inverse of the N*(N−1)/2 comparison result values; a parallel adder circuit to perform parallel additions of the bits in each row to generate N unique result values; and sorting circuitry to index into the N unique result values to return the sorted order.

公开(公告)号：US12045172B2

公开(公告)日：2024-07-23

申请号：US17987020

申请日：2022-11-15

申请人： Texas Instruments Incorporated

发明人： Mujibur Rahman ,  Timothy David Anderson

IPC分类号： G06F7/487 ,  G06F7/24 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06

CPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/3822 ,  G06F11/10 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

摘要： A method is provided that includes performing, by a processor in response to a floating point multiply instruction, multiplication of floating point numbers, wherein determination of values of implied bits of leading bit encoded mantissas of the floating point numbers is performed in parallel with multiplication of the encoded mantissas, and storing, by the processor, a result of the floating point multiply instruction in a storage location indicated by the floating point multiply instruction.

公开(公告)号：US20240242523A1

公开(公告)日：2024-07-18

申请号：US18097961

申请日：2023-01-17

申请人： Yuri P. Garbuzov

发明人： Yuri P. Garbuzov

IPC分类号： G06F7/24 ,  G01F15/063 ,  G06V30/148

CPC分类号： G06F7/24 ,  G01F15/063 ,  G06V30/153

摘要： A meter readout on a meter has digits including a first digit, a second digit, etc. A sequence of images of the meter is obtained. The images include images of the digits in the meter readout. Automated recognition of the digits in the images result in likelihood arrays indicating the likelihoods for the digit values for the digits imaged in the meter images. Short chains of digit values are identified and spliced together to form a series of single digit, two-digit, three-digits, etc. paths that are built up based on the likelihood arrays. Various criteria are used to discard most of the chains and thereby avoid the combinatorial explosion of possible paths and thereby produce reliable meter readings without consuming considerable computational resources.

公开(公告)号：US12032490B2

公开(公告)日：2024-07-09

申请号：US18073313

申请日：2022-12-01

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Timothy David Anderson ,  Mujibur Rahman

IPC分类号： G06F12/10 ,  G06F7/24 ,  G06F7/487 ,  G06F7/499 ,  G06F7/53 ,  G06F7/57 ,  G06F9/30 ,  G06F9/32 ,  G06F9/345 ,  G06F9/38 ,  G06F9/48 ,  G06F11/00 ,  G06F11/10 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/1045 ,  G06F17/16 ,  H03H17/06 ,  G06F15/78

CPC分类号： G06F12/1045 ,  G06F7/24 ,  G06F7/487 ,  G06F7/4876 ,  G06F7/49915 ,  G06F7/53 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/30072 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/32 ,  G06F9/345 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3856 ,  G06F9/3867 ,  G06F9/3887 ,  G06F9/48 ,  G06F11/00 ,  G06F11/1048 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1009 ,  G06F17/16 ,  H03H17/0664 ,  G06F9/30018 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3822 ,  G06F11/10 ,  G06F15/7807 ,  G06F15/781 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602 ,  G06F2212/68

摘要： A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values are sorted in an order indicated by the vector sort instruction, and storing the sorted vector in a storage location.

公开(公告)号：US20240104098A1

公开(公告)日：2024-03-28

申请号：US18534912

申请日：2023-12-11

申请人： Ocient Holdings LLC

发明人： George Kondiles ,  Jason Arnold

IPC分类号： G06F16/2453 ,  G06F3/06 ,  G06F7/24 ,  G06F9/4401 ,  G06F9/50 ,  G06F11/10 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/17 ,  G06F16/22 ,  G06F16/23 ,  G06F16/242 ,  G06F16/2455 ,  G06F16/2457 ,  G06F16/2458 ,  G06F16/27 ,  G06F16/901 ,  H03M7/30 ,  H04L67/10

CPC分类号： G06F16/24542 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/068 ,  G06F7/24 ,  G06F9/4406 ,  G06F9/5016 ,  G06F9/5027 ,  G06F9/5061 ,  G06F11/1004 ,  G06F11/1044 ,  G06F11/1076 ,  G06F12/0893 ,  G06F12/109 ,  G06F16/1727 ,  G06F16/22 ,  G06F16/2246 ,  G06F16/2282 ,  G06F16/2365 ,  G06F16/244 ,  G06F16/2445 ,  G06F16/2453 ,  G06F16/24553 ,  G06F16/24573 ,  G06F16/2458 ,  G06F16/278 ,  G06F16/901 ,  G06F16/9017 ,  H03M7/30 ,  H04L67/10 ,  G06F3/067 ,  G06F16/24547 ,  G06F2211/1011 ,  G06F2212/608

摘要： A node of a computing system includes a main memory and a plurality of processing core resources. The main memory includes a computing device section and a database section. The computing device section includes a computing device operating system area and a computing device general area. The database section includes a database section that includes a database operating system area, a disk area, a network area, and a database general area. The database operating system area allocates at least one portion of the main memory for database operations that is locked from access by the computing device operating system area.

公开(公告)号：US11922566B2

公开(公告)日：2024-03-05

申请号：US17516274

申请日：2021-11-01

申请人： Imagination Technologies Limited

发明人： Lorenzo Belli ,  Robert Brigg

IPC分类号： G06T15/40 ,  G06F7/24 ,  G06F9/48 ,  G06T1/60 ,  G06T7/50 ,  G06T15/20 ,  G06T17/10

CPC分类号： G06T15/405 ,  G06F7/24 ,  G06F9/4881 ,  G06T1/60 ,  G06T7/50 ,  G06T15/20 ,  G06T15/40 ,  G06T17/10 ,  G06T2207/10028 ,  G06T2207/20021

摘要： Methods and coarse depth test logic perform coarse depth testing in a graphics processing system in which a rendering space is divided into a plurality of tiles. A depth range for a tile identifies a depth range based on primitives previously processed. A determination is made based on the depth range for the tile as to whether all or a portion of a primitive is hidden in the tile. If at least a portion of the primitive is not hidden in the tile, a determination is made as to whether the primitive or a primitive fragment thereof has better depth than the primitives previously processed for the tile. If so, the primitive or the primitive fragment is identified as not requiring a read of a depth buffer to perform full resolution depth testing, such that a determination that at least a portion of the primitive is hidden in the tile causes full resolution depth testing not to be performed on at least that portion of the primitive.