Process for Scaling a Gate Length

    公开(公告)号:US20210151593A1

    公开(公告)日:2021-05-20

    申请号:US16950519

    申请日:2020-11-17

    Applicant: IMEC VZW

    Abstract: A method comprising: providing a semiconductor structure including: a channel, a barrier, a non-conductive structure over the barrier, the non-conductive structure including a cavity having sidewalls separated by a first distance, providing a first non-conductive layer conformally over the non-conductive structure, thereby covering the sidewalls and the bottom surface of the cavity, etching the first non-conductive layer in such a way that it is removed from at least part of the bottom surface but still covers the sidewalls, etching through the bottom surface at most until the channel is reached, by using the first non-conductive layer covering the sidewalls as a mask, thereby forming an opening in the bottom surface of the non-conductive structure, the opening having sidewalls separated by a second distance, smaller than the first distance, and completely removing the first non-conductive layer.

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