公开(公告)号：US20210151593A1

公开(公告)日：2021-05-20

申请号：US16950519

申请日：2020-11-17

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  AliReza Alian ,  Uthayasankaran Peralagu

IPC: H01L29/778 ,  H01L29/66

Abstract: A method comprising: providing a semiconductor structure including: a channel, a barrier, a non-conductive structure over the barrier, the non-conductive structure including a cavity having sidewalls separated by a first distance, providing a first non-conductive layer conformally over the non-conductive structure, thereby covering the sidewalls and the bottom surface of the cavity, etching the first non-conductive layer in such a way that it is removed from at least part of the bottom surface but still covers the sidewalls, etching through the bottom surface at most until the channel is reached, by using the first non-conductive layer covering the sidewalls as a mask, thereby forming an opening in the bottom surface of the non-conductive structure, the opening having sidewalls separated by a second distance, smaller than the first distance, and completely removing the first non-conductive layer.

公开(公告)号：US20180182849A1

公开(公告)日：2018-06-28

申请号：US15829753

申请日：2017-12-01

Applicant: IMEC VZW

Inventor： AliReza Alian ,  Salim El Kazzi

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L21/02

CPC classification number: H01L29/0676 ,  H01L21/02107 ,  H01L29/0649 ,  H01L29/408 ,  H01L29/42316 ,  H01L29/4232 ,  H01L29/66666 ,  H01L29/7827

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure. The FET device additionally includes a control electrode configured to apply an electric field across the thin layer of 2D material to cause a change in the conductivity of the thin layer of 2D material. The FET device further includes at least one stack of materials configured to provide different regions of band bending in the thin layer of 2D material by capacitive coupling.

公开(公告)号：US10608085B2

公开(公告)日：2020-03-31

申请号：US15829753

申请日：2017-12-01

Applicant: IMEC VZW

Inventor： AliReza Alian ,  Salim El Kazzi

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: The disclosed technology relates generally to semiconductor devices, and more particularly to field-effect transistors (FETs) comprising nanostructures, such as nanowires, fins, and two dimensional materials. In an aspect, a FET device comprises a substrate having an insulating surface and a vertical structure extending in a direction substantially perpendicular to the insulating surface, where the vertical structure has at least outer surfaces formed of an insulating material. The FET device additionally includes a thin layer of two-dimensional (2D) material enveloping the vertical structure and at least part of the insulating surface. The FET device additionally includes two electrodes in electrical contact with the thin layer of 2D material, where one of the electrodes is formed on top of the vertical structure. The FET device additionally includes a control electrode configured to apply an electric field across the thin layer of 2D material to cause a change in the conductivity of the thin layer of 2D material. The FET device further includes at least one stack of materials configured to provide different regions of band bending in the thin layer of 2D material by capacitive coupling.

公开(公告)号：US09741848B2

公开(公告)日：2017-08-22

申请号：US15337776

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Mohammad Ali Pourghaderi ,  AliReza Alian

IPC: H01L29/02 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7831 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/512 ,  H01L29/7391

Abstract: A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

公开(公告)号：US09704992B2

公开(公告)日：2017-07-11

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/76 ,  H01L29/94 ,  H01L29/78 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

公开(公告)号：US20170179283A1

公开(公告)日：2017-06-22

申请号：US15337776

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Mohammad Ali Pourghaderi ,  AliReza Alian

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/7831 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/512 ,  H01L29/7391

Abstract: A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure comprises a source region being n-type or p-type doped, a drain region oppositely doped than the source region and an intrinsic or lowly doped channel region situated between the source region and the drain region. The TFET further comprises a reference gate structure covering the channel region and a source-side gate structure aside of the reference gate structure wherein the work function and/or electrostatic potential of the source-side gate structure and the reference work function and/or electrostatic potential of the reference gate structure are selected for allowing the tunneling mechanism of the TFET device in operation to occur at the interface or interface region between the source-side gate structure and the reference gate structure in the channel region.

公开(公告)号：US20170170314A1

公开(公告)日：2017-06-15

申请号：US15337728

申请日：2016-10-28

Applicant: IMEC VZW

Inventor： Anne Verhulst ,  Devin Verreck ,  AliReza Alian

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/36

CPC classification number: H01L29/7835 ,  H01L29/0834 ,  H01L29/36 ,  H01L29/41775 ,  H01L29/4234 ,  H01L29/42356 ,  H01L29/42364 ,  H01L29/7391 ,  H01L29/7831

Abstract: A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.