公开(公告)号：US20250125291A1

公开(公告)日：2025-04-17

申请号：US18685402

申请日：2023-02-21

Applicant: MICLEDI MICRODISPLAYS BV ,  IMEC VZW

Inventor： Emmanuel LE BOULBAR ,  Soeren STEUDEL ,  Johan VERTOMMEN ,  Robert MILLER ,  Joeri DE VOS ,  Stefaan VAN HUYLENBROECK ,  Eric BEYNE ,  Liesbeth WITTERS

IPC: H01L23/00

Abstract: A semiconductor product is provided. The semiconductor product comprises a first wafer (21) comprising a first active pad array (21a), and at least a second wafer (22) comprising at least a second active pad array (22a). In this context, the first wafer (21) and the at least one second wafer (22) are bonded together. In addition to this, the first wafer (21) and/or the at least one second wafer (22) comprises a transition area (23) being directly adjacent to the first active pad array (21a) and/or the at least one second active pad array (22a).

公开(公告)号：US20200212205A1

公开(公告)日：2020-07-02

申请号：US16719852

申请日：2019-12-18

Applicant: IMEC vzw

Inventor： Geert Eneman ,  Bartlomiej PAWLAK ,  Liesbeth WITTERS ,  Geoffrey POURTOIS

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

Abstract: According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US20150076620A1

公开(公告)日：2015-03-19

申请号：US14484070

申请日：2014-09-11

Applicant: IMEC VZW

Inventor： Niamh WALDRON ,  Liesbeth WITTERS

IPC: H01L27/092 ,  H01L29/267 ,  H01L21/762 ,  H01L29/04 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/20 ,  H01L29/161

CPC classification number: H01L27/0922 ,  H01L21/762 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/20 ,  H01L29/267

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to different types of transistors having different channel materials. In one aspect, a method of fabricating a semiconductor device includes providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a direction. The method additionally includes forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions. The method additionally includes forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type. The method further includes removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures and filling the trenches with a III-V material.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及具有不同通道材料的不同类型的晶体管。 一方面，一种制造半导体器件的方法包括提供包括硅衬底的衬底，所述衬底具有取向为{100}晶面并具有沿<100>方向取向的凹口的主表面。 该方法还包括通过使包围硅突起的主表面的部分凹陷来在第一预定区域中形成多个硅突起。 该方法还包括形成与硅突起相邻的浅沟槽隔离（STI）结构，以电隔离硅突起，由此限定第一类型晶体管的沟道区。 该方法还包括去除硅突起的至少上部，从而在相邻STI结构之间形成沟槽并用III-V材料填充沟槽。