公开(公告)号：US10211847B1

公开(公告)日：2019-02-19

申请号：US15853873

申请日：2017-12-25

Applicant: Industrial Technology Research Institute

Inventor： Yung-Hui Chung ,  Bo-Wei Chen

IPC: H03M1/46

Abstract: A successive approximation register (SAR) analog-digital converter (ADC) and a method for operating the same are provided. The SAR ADC includes a first capacitor DAC (CDAC), a comparator and a controller. The first CDAC receives and samples an analog input signal to generate a first voltage. The comparator compares the first voltage with a comparison reference voltage to generate a first comparison result. In a k-th iteration of at least two iterations, the controller switches a k-th switching capacitor set from a first state to a second state, such that the first CDAC generates a second voltage, and the comparator compares the second voltage with the comparison reference voltage to generate a second comparison result. The controller determines a window region and determines whether the k-th switching capacitor set is switched back to the first state according to the first comparison result and the second comparison result.

公开(公告)号：US08957706B2

公开(公告)日：2015-02-17

申请号：US13727533

申请日：2012-12-26

Applicant: Industrial Technology Research Institute

Inventor： Bo-Wei Chen

IPC: H03K5/22

CPC classification number: H03K5/22

Abstract: The present disclosure provides a dynamic comparator with equalization function including a preamplifier, switched latch and dynamic transconductance circuit. The preamplifier amplifies input signals of the dynamic comparator. The dynamic transconductance circuit is inserted between the preamplifier and the switched latch for operating in a reset mode or a comparison mode. When operating in the reset mode, the dynamic transconductance circuit in conjunction with the switched latch performs voltage equalization of output signals of the switched latch, or when operating in the comparison mode, the dynamic transconductance circuit in conjunction with the switched latch receives the output signals generated by the preamplifier and carries out signal transconductance. The switched latch generates output signals as a comparison result of the dynamic comparator based on the transconductance signals generated by the dynamic transconductance circuit. The present disclosure provides a dynamic comparator that reduces the power consumption and increasing the operating speed.

Abstract translation: 本公开提供具有均衡功能的动态比较器，包括前置放大器，开关锁存器和动态跨导电路。 前置放大器放大动态比较器的输入信号。 动态跨导电路插入在前置放大器和开关锁存器之间，用于在复位模式或比较模式下工作。 当在复位模式下操作时，动态跨导电路结合开关锁存器执行开关锁存器的输出信号的电压均衡，或当在比较模式下工作时，动态跨导电路与开关锁存器一起接收输出信号 由前置放大器产生并执行信号跨导。 开关锁存器基于动态跨导电路产生的跨导信号，产生作为动态比较器的比较结果的输出信号。 本公开提供了一种动态比较器，其降低功耗并提高操作速度。

公开(公告)号：US20250168798A1

公开(公告)日：2025-05-22

申请号：US18389786

申请日：2023-12-20

Applicant: Industrial Technology Research Institute

Inventor： Chai-Hien Gan ,  Bo-Wei Chen

IPC: H04W60/00 ,  H04W8/26

Abstract: Disclosed is method for identifying a user equipment (UE), including: generating a RAN UE ID corresponding to the UE through a base station; when the UE submits a register request with an enrichment information provider, receiving a packet of the UE through the base station, obtaining the IP address corresponding to the UE based on the packet and transmitting the packet to a core network; transmitting the IP address and the RAN UE ID corresponding to the UE to a RIC through the base station; establishing a mapping association associated with the IP address and the RAN UE ID corresponding to the UE in a mapping table through the RIC; and transmitting the packet to the enrichment information provider through the core network, and obtaining the IP address corresponding to the UE based on the packet and accepting the register request with the IP address through the enrichment information provider.

公开(公告)号：US09190987B2

公开(公告)日：2015-11-17

申请号：US13798129

申请日：2013-03-13

Applicant: Industrial Technology Research Institute

Inventor： Chia-Ming Tsai ,  Bo-Jyun Kuo ,  Bo-Wei Chen

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356173

Abstract: A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.

Abstract translation: 提供了一种闩锁装置及其应用。 锁存装置由锁存电路和可切换DC块单元组成。 可切换DC块单元耦合到锁存电路，并且被配置为：在闩锁装置执行锁存操作之前，隔离锁存电路中的交叉耦合路径并存储电压差; 并且当锁存装置执行锁存操作时，提供随时间变化的存储电压以增加锁存电路中的至少一个晶体管的过驱动电压（增加晶体管跨导），使得锁存装置在低电源下保持高速运行 电压。

公开(公告)号：US09395746B2

公开(公告)日：2016-07-19

申请号：US14729063

申请日：2015-06-03

Applicant: Industrial Technology Research Institute

Inventor： Yung-Hui Chung ,  Bo-Wei Chen

IPC: G06F1/04 ,  G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08

Abstract: A signal comparison apparatus and a method of controlling the same are provided. The signal comparison apparatus includes a first comparator, a self-timed clock generator and a controller. The first comparator is controlled by a start signal to compare differences of first input signals and generate output signals. The self-timed clock generator receives the output signals to generate a self-timed clock signal. The controller receives the self-timed clock signal and calculates a time interval of the self-timed clock signal which responds to the first input signals of the first comparator, and determines whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal. When the time interval is equal to or larger than the threshold time, the controller outputs the metastable detection signal as the start signal, such that the first comparator continue comparing the next differences of the first input signals.

Abstract translation: 提供了一种信号比较装置及其控制方法。 信号比较装置包括第一比较器，自定时钟发生器和控制器。 第一比较器由起始信号控制，以比较第一输入信号的差异并产生输出信号。 自定时钟发生器接收输出信号以产生自定时钟信号。 控制器接收自定时钟信号并计算响应于第一比较器的第一输入信号的自定时钟信号的时间间隔，并且确定时间间隔是否等于或大于生成阈值时间 亚稳态检测信号。 当时间间隔等于或大于阈值时间时，控制器输出亚稳检测信号作为起始信号，使得第一比较器继续比较第一输入信号的下一个差。

公开(公告)号：US20140132323A1

公开(公告)日：2014-05-15

申请号：US13798129

申请日：2013-03-13

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chia-Ming Tsai ,  Bo-Jyun Kuo ,  Bo-Wei Chen

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356173

Abstract: A latch apparatus and applications thereof are provided. The latch apparatus consists of a latch circuit and a switchable DC block unit. The switchable DC block unit is coupled to the latch circuit, and configured to: isolate a cross-coupling path in the latch circuit and store a voltage difference before the latch apparatus performs the latching operation; and when the latch apparatus performs the latching operation, provide the stored voltage varying with time to increase the overdrive voltage of at least one transistor in the latch circuit (increase the transistor transconductance), so that the latch apparatus maintains high speed operation at low supply voltage.

Abstract translation: 提供了一种闩锁装置及其应用。 锁存装置由锁存电路和可切换DC块单元组成。 可切换DC块单元耦合到锁存电路，并且被配置为：在闩锁装置执行锁存操作之前，隔离锁存电路中的交叉耦合路径并存储电压差; 并且当锁存装置执行锁存操作时，提供随时间变化的存储电压以增加锁存电路中的至少一个晶体管的过驱动电压（增加晶体管跨导），使得锁存装置在低电源下保持高速运行 电压。

公开(公告)号：US20160161978A1

公开(公告)日：2016-06-09

申请号：US14729063

申请日：2015-06-03

Applicant: Industrial Technology Research Institute

Inventor： Yung-Hui Chung ,  Bo-Wei Chen

IPC: G06F1/10

CPC classification number: G06F1/10 ,  G06F1/08

Abstract: A signal comparison apparatus and a method of controlling the same are provided. The signal comparison apparatus includes a first comparator, a self-timed clock generator and a controller. The first comparator is controlled by a start signal to compare differences of first input signals and generate output signals. The self-timed clock generator receives the output signals to generate a self-timed clock signal. The controller receives the self-timed clock signal and calculates a time interval of the self-timed clock signal which responds to the first input signals of the first comparator, and determines whether the time interval is equal to or larger than a threshold time to generate a metastable detection signal. When the time interval is equal to or larger than the threshold time, the controller outputs the metastable detection signal as the start signal, such that the first comparator continue comparing the next differences of the first input signals.

Abstract translation: 提供了一种信号比较装置及其控制方法。 信号比较装置包括第一比较器，自定时钟发生器和控制器。 第一比较器由起始信号控制，以比较第一输入信号的差异并产生输出信号。 自定时钟发生器接收输出信号以产生自定时钟信号。 控制器接收自定时钟信号并计算响应于第一比较器的第一输入信号的自定时钟信号的时间间隔，并且确定时间间隔是否等于或大于生成阈值时间 亚稳态检测信号。 当时间间隔等于或大于阈值时间时，控制器输出亚稳检测信号作为起始信号，使得第一比较器继续比较第一输入信号的下一个差。

公开(公告)号：US20150061730A1

公开(公告)日：2015-03-05

申请号：US14097267

申请日：2013-12-05

Applicant: Industrial Technology Research Institute

Inventor： Chia-Ming Tsai ,  Bo-Jyun Kuo ,  Bo-Wei Chen

IPC: H03K3/356

CPC classification number: H03K3/356034

Abstract: A latch, an operation method of the latch, and a comparator using the latch are disclosed. The latch includes first and second cross-coupled pairs and first and second transistor pairs. First terminals of the first and second current paths of the first cross-coupled pair are respectively coupled to first terminals of the first and second transistors of the first transistor pair. First terminals of the third and fourth current paths of the second cross-coupled pair are respectively coupled to first terminals of the third and fourth transistors of the second transistor pair. Control terminals of the third and fourth transistors are respectively coupled to the first and second current paths. Control terminals of the first and second transistors are respectively coupled to the third and fourth current paths.

Abstract translation: 公开了锁存器，锁存器的操作方法和使用该锁存器的比较器。 锁存器包括第一和第二交叉耦合对以及第一和第二晶体管对。 第一交叉耦合对的第一和第二电流路径的第一端分别耦合到第一晶体管对的第一和第二晶体管的第一端。 第二交叉耦合对的第三和第四电流路径的第一端分别耦合到第二晶体管对的第三和第四晶体管的第一端。 第三和第四晶体管的控制端分别耦合到第一和第二电流路径。 第一和第二晶体管的控制端分别耦合到第三和第四电流路径。