公开(公告)号：US11314569B2

公开(公告)日：2022-04-26

申请号：US16729288

申请日：2019-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Li-Ren Huang ,  Chi-Chun Hsu

IPC: G06F11/00 ,  G06F11/07

Abstract: A processor capable of changing redundant processing node comprises a plurality of processing nodes and a plurality of comparators. The plurality of processing nodes comprises a first processing node, a second processing node, and a third processing node, wherein the first processing node performs a first computation, the second processing node selectively performs the first computation or a second computation, and the third processing node performs the second computation. The plurality of comparators comprises a first comparator and a second comparator, wherein the first comparator connects to the first and second processing nodes to compare whether the results of the first computation performed by the first and second processing nodes are identical, and the second comparator connects to the second and third processing nodes to compare whether results of the second computation performed by the second and third processing nodes are identical.

公开(公告)号：US08867289B2

公开(公告)日：2014-10-21

申请号：US13727046

申请日：2012-12-26

Applicant: Industrial Technology Research Institute

Inventor： Chun-Yen Wu ,  Chi-Chun Hsu ,  Po-Sen Huang ,  Li-Ren Huang ,  Wen-Dar Hsieh

IPC: G11C7/00 ,  G11C29/00

CPC classification number: G11C29/00 ,  G11C29/08 ,  G11C29/16 ,  G11C2029/0401

Abstract: A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit.

Abstract translation: 提供了具有嵌入式非易失性存储器和芯片的芯片的测试方法。 重映射电路和非易失性存储器连接到处理器。 非易失性存储器具有测试区域和被测试区域。 测试区域存储测试程序，被测区域存储被测数据。 当处理器对芯片进行测试时，处理器输出原始指令地址，并且重新映射电路重新映射原始指令地址以生成重新映射的指令地址。 处理器读取测试区域中的测试程序，并执行测试程序以读取被测区域内的数据，并执行切换逻辑电路的测试。