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公开(公告)号：US10374842B2
公开(公告)日：2019-08-06
申请号：US16212169
申请日：2018-12-06
Applicant: INPHI CORPORATION
Inventor： Karim Abdelhalim , Michael Le , Haidang Lin
Abstract: The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.
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公开(公告)号：US10187230B1
公开(公告)日：2019-01-22
申请号：US15699882
申请日：2017-09-08
Applicant: INPHI CORPORATION
Inventor： Karim Abdelhalim , Michael Le , Haidang Lin
Abstract: The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well.
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